I am looking to simulate QPSI on FlexIO, using the MIMXRT1170-EVKB.
It appears that board examples for FlexIO (driver_examples\flexio\spi) only include LPSPI examples for a single lane SPI (PCS, SOUT, SIN, and CLK).
Are there any examples available on how to simulate QPSI (PCS, DATA[0, 1, 2, 3], and CLK) via FlexIO?
Previous post Solved: RT1011 QSPI implementation - NXP Community appears to indicate that QSPI is possible with LPSPI and with FlexIO. I see where LSPI can be configured to do QSPI? But how can I use FlexIO to simulate QSPI?
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After looking at FlexIO example for a traditional SPI implementation, I have a question about the FlexIO peripheral and how the shift register(s) work.
Knowing that QSPI mode requires 4 data pins (Rx or Tx), will FLEXIO require the use of 4 shift registers to receive or send each bit on each data pin? Also, for implementing QSPI mode, can one FlexIO shift register be configured to distribute (receive or send) each bit onto the 4 data pins in QSPI bit order? I'm thinking that the former (4 register approach) is easier to do (if not only option).
Sorry we do not have sample for that