RT1052 with 64MB SDRAM causes unaligned memory Hard Fault

[kwolley]

Hello, 

I am using the RT1052 with 64MB of external SDRAM (ISSI 42S86400F-6TL) on an 8-bit data bus.  Attempting to access to data across banks trips an Unaligned (8) - Unaligned access Usage Fault.   Why?

Example below is configured to run out of internal RAM.

SEMC configuration is as follows:

#define EXAMPLE_SEMC_CLK_FREQ      	CLOCK_GetFreq(kCLOCK_SemcClk)
status_t BOARD_InitSEMC(void)
{
semc_config_t config;
    semc_sdram_config_t sdramconfig;
    uint32_t clockFrq = EXAMPLE_SEMC_CLK_FREQ;

    /* Initializes the MAC configure structure to zero. */
    memset(&config, 0, sizeof(semc_config_t));
    memset(&sdramconfig, 0, sizeof(semc_sdram_config_t));

    /* Initialize SEMC. */
    SEMC_GetDefaultConfig(&config);
    config.dqsMode = kSEMC_Loopbackinternal; /* For more accurate timing. */
    SEMC_Init(SEMC, &config);

    /* Configure SDRAM. checked by KW 12/07 */
    sdramconfig.csxPinMux           = kSEMC_MUXCSX0;
    sdramconfig.address             = 0x80000000;
    sdramconfig.memsize_kbytes      = 64 * 1024; /* 64MB = 64*1024*1KBytes*/
    sdramconfig.portSize            = kSEMC_PortSize8Bit;
    sdramconfig.burstLen            = kSEMC_Sdram_BurstLen1;
    sdramconfig.columnAddrBitNum    = kSEMC_SdramColunm_11bit;
    sdramconfig.casLatency          = kSEMC_LatencyThree;
    sdramconfig.tPrecharge2Act_Ns   = 21; /* Trp 3 cycles, 7 ns/ea (min 15ns) */
    sdramconfig.tAct2ReadWrite_Ns   = 21; /* Trcd 3 cycles, 7 ns/ea (min 15ns)  */
    sdramconfig.tRefreshRecovery_Ns = 67; /* Use the maximum of the (Trfc , Txsr). */
    sdramconfig.tWriteRecovery_Ns   = 12; /* 12ns ? */
    /* The minimum cycle of SDRAM CLK off state. CKE is off in self refresh at a minimum period tRAS.*/
    sdramconfig.tCkeOff_Ns			= 42;
    sdramconfig.tAct2Prechage_Ns       = 42; /* Tras 6 cycles, 7 ns/ea (min 37)*/
    sdramconfig.tSelfRefRecovery_Ns    = 67; /* Txsr */
    sdramconfig.tRefresh2Refresh_Ns    = 63; /* Trc  9 cycles */
    sdramconfig.tAct2Act_Ns            = 63; /* same as above */
    sdramconfig.tPrescalePeriod_Ns     = (uint32_t) (160 * (1000000000 / clockFrq) + 1 );
    sdramconfig.refreshPeriod_nsPerRow = (uint32_t) (64 * 1000000 / 8192) + 1; /* 64ms/8192 */
    sdramconfig.refreshUrgThreshold    = sdramconfig.refreshPeriod_nsPerRow;
    sdramconfig.refreshBurstLen        = 1;
    return SEMC_ConfigureSDRAM(SEMC, kSEMC_SDRAM_CS0, &sdramconfig, EXAMPLE_SEMC_CLK_FREQ);
}

Project attached with noted failure points.  

Any insight would be greatly appreciated.

Kara

[kwolley]

Hi @mark82 ,

I have not found a reasonable explanation for this.  My current workaround is to change the stack offset and use half the memory space (not ideal).   For example in Properties -> C/C++ Build -> Settings -> MCU C++ Linker -> Managed Linger Script :

I hope this helps.  Let me know if you solve the issue.

[Kan_Li]

Hi @kwolley ,

I agree @mark82 's solution. Does it work for your case? 

Have a great day,
Kan

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!
- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

[mark82]

Yes, I can use half memory successfully but that doesn't suit my case. I need to access the whole memory. So, it seems it is still unresolved here...  

The curious thing is that tests of writing and reading the whole chip are successfull.. The thing is tripped by an unaligned access on the second half of chip...

[kwolley]

@mark82, I agree this is still unresolved. Perhaps someone else can assist us in this.

[mark82 · Accepted solution]

Ehi. I think I got it. 

You have to enable the MPU for the entire region you need. 

If you have SDK example, checkout the board.c file, function BOARD_ConfigMPU.

For me, it worked changing from ARM_MPU_REGION_SIZE_32MB to ARM_MPU_REGION_SIZE_64MB

here:

    /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
    MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U);
    MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);

Enabling the MPU for the external SDRAM memory makes it a Normal Device which prevents hardfault when accessing memory unaliegned-wise.

More details are available in ARM docs for developers.

Hope it solves for you, too.

[kwolley]

@mark82, thank you for the assist! I believe this worked for me as well.

[mark82]

Great! Glad to hear that!

[mark82]

Hello. I'm facing a very similar issue.

RT1052, external SDRAM memory chip of 64MB (ISSI IS42S16320F). When attemptin to access banks over the half of the memory, I get unaligned access fault which escalates to hardfault.

Have you by chance solved or understood the cause?

Thanks.