The chip I am using is RT1052, which is a self-developed board. The PHY chip is LAN8720
Software environment: I have ported it https://github.com/nxp-appcodehub/an-ethernet-lwip-ptpd-imxrt/tree/main/evkbimxrt1050_lwip_ptpd_free...
The PTPD code in, the code on GitHub was developed under NXP's IDE, and I ported it to MDK. Connect to two boards using RJ45. Among them, global macros IMX_RT1xxx, HAVE-SYS_TIMEX_H are defined
Problem description:
Tests have found that the PPS signal output during synchronization has a minimum difference of about 32ms between the master and slave, and the slave will suddenly exhibit a spike that does not match the 1Hz signal, resulting in a significant time error compared to the actual official test. Here are the signals I captured using a logic analyzer:
In the attachment, there is a LOG file with the PTPD_DBG macro opened.
May I ask if it was due to my unsuccessful transplantation or other reasons? If you need the key code, I can provide analysis.
