Hello Wigros,
I parsed out the register values, and followed the math in the Clock Config note that you forwarded. I arrive at the same 109.2 MHz clock value that was computed by the MCU API functions. To confirm my understanding, a few follow up questions:
1. does this mean that 109.2MHz is the clock being applied to the SDRAM?
2. is it safe to change these various clock dividers to arrive at a different frequency, and if so what is the acceptable range?
3. the math: "sdramconfig.tCkeOff_Ns = (1000000000 / clockFrq);" rounds down, should I be concerned that the setting might be too aggressive?
Thanks again for your help!
Joshua