I couldn't find a note on how to configure the clock for specific SDRAM part, but noticed that in in the SEMC example there are a couple of clues:
if EXAMPLE_SEMC_CLK_FREQ is printed the value is: 109241376 -- I was anticipating 132MHz (based on the comment and the functionality described in the application note: https://www.nxp.com/docs/en/application-note/AN12077.pdf)
Based on experimentation with the value 'N' passed as the second argument to: CLOCK_SetDiv(kCLOCK_SemcDiv, N) -- where N ranges from 1..7, EXAMPLE_SEMC_CLK_FREQ ranges from: 163862064..40965516
Many thanks in advance!
Hello Joshua,
See the link, please!
https://community.nxp.com/docs/DOC-340813
After understanding how to configure registers related to SDRAM clock, go back to configure it in SDK.
Have a nice day!
TIC weidong sun
Hello Wigros,
I parsed out the register values, and followed the math in the Clock Config note that you forwarded. I arrive at the same 109.2 MHz clock value that was computed by the MCU API functions. To confirm my understanding, a few follow up questions:
1. does this mean that 109.2MHz is the clock being applied to the SDRAM?
2. is it safe to change these various clock dividers to arrive at a different frequency, and if so what is the acceptable range?
3. the math: "sdramconfig.tCkeOff_Ns = (1000000000 / clockFrq);" rounds down, should I be concerned that the setting might be too aggressive?
Thanks again for your help!
Joshua
Thanks TIC -- this is great information! I will study it.