Thanks for your reply.
After confirming, 4-bit half-duplex transfers are useful for interfacing to QuadSPI memory devices, and at least one bit (Transmit Data
Mask (TCR[TXMSK] or Receive Data Mask TCR[RXMSK]) must
also be set.
However, when set TCR[RXMSK]), receive data is not stored in receive FIFO, and according to Table 47-10. LPSPI Interrupts and DMA Requests, the mechanism is unable to trigger the DMA request.

Sorry for the previous reply bring inconvenience to you.
Have a great day,
TIC
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