RT 1170 Dual SDRAM 16bit connection

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RT 1170 Dual SDRAM 16bit connection

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MaxM
Contributor I

Planning on using Dual 256Mbit SDRAM with RT1172, instead of single 512MBit chip, but due to GPIO pins shortage I want to use 16bit databus.

Reference manual only mentions that it is possible with CS0 and CS1, I assume all other lines between 2 chips are connected in parallel .

 

MIMXRT1170-EVKB has 32bit databus connection, where the address and command groups connected in parallel, but the 16bit databuses are separate.

 

Could you confirm that such 16bit Dual SDRAM connection is possible and provide a schematics example if possible.

 

Also, do you have a benchmarking information on single 16bit SDRAM data transfer rate versus Dual SDRAM 16bit

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EdwinHz
NXP TechSupport
NXP TechSupport

Hi @MaxM,

Unfortunately, we do not have any reference schematics or benchmarks for a Dual SDRAM configuration on the RT1170, but I can say that you are definitely correct on the connection. All lines except CS0 and CS1 are connected in parallel, and the CS lines are connected to each of the SDRAMs.

BR,
Edwin. 

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EdwinHz
NXP TechSupport
NXP TechSupport

Hi @MaxM,

Unfortunately, we do not have any reference schematics or benchmarks for a Dual SDRAM configuration on the RT1170, but I can say that you are definitely correct on the connection. All lines except CS0 and CS1 are connected in parallel, and the CS lines are connected to each of the SDRAMs.

BR,
Edwin. 

%3CLINGO-SUB%20id%3D%22lingo-sub-1985011%22%20slang%3D%22en-US%22%20mode%3D%22CREATE%22%3ERT%201170%20Dual%20SDRAM%2016bit%20connection%3C%2FLINGO-SUB%3E%3CLINGO-BODY%20id%3D%22lingo-body-1985011%22%20slang%3D%22en-US%22%20mode%3D%22CREATE%22%3E%3CP%3EPlanning%20on%20using%20Dual%20256Mbit%20SDRAM%20with%20RT1172%2C%20instead%20of%20single%20512MBit%20chip%2C%20but%20due%20to%20GPIO%20pins%20shortage%20I%20want%20to%20use%2016bit%20databus.%3C%2FP%3E%3CP%3EReference%20manual%20only%20mentions%20that%20it%20is%20possible%20with%20CS0%20and%20CS1%2C%20I%20assume%20all%20other%20lines%20between%202%20chips%20are%20connected%20in%20parallel%20.%3C%2FP%3E%3CBR%20%2F%3E%3CP%3E%3CSPAN%20class%3D%22%22%3EMIMXRT1170-EVKB%3C%2FSPAN%3E%20has%2032bit%20databus%20connection%2C%20where%20the%20address%20and%20command%20groups%20connected%20in%20parallel%2C%20but%20the%2016bit%20databuses%20are%20separate.%3C%2FP%3E%3CBR%20%2F%3E%3CP%3ECould%20you%20confirm%20that%20such%2016bit%20Dual%20SDRAM%20connection%20is%20possible%20and%20provide%20a%20schematics%20example%20if%20possible.%3C%2FP%3E%3CBR%20%2F%3E%3CP%3EAlso%2C%20do%20you%20have%20a%20benchmarking%20information%20on%20single%2016bit%20SDRAM%20data%20transfer%20rate%20versus%20Dual%20SDRAM%2016bit%3C%2FP%3E%3C%2FLINGO-BODY%3E%3CLINGO-LABS%20id%3D%22lingo-labs-1985011%22%20slang%3D%22en-US%22%20mode%3D%22CREATE%22%3E%3CLINGO-LABEL%3Ei.MXRT%20101x%3C%2FLINGO-LABEL%3E%3C%2FLINGO-LABS%3E%3CLINGO-SUB%20id%3D%22lingo-sub-1986436%22%20slang%3D%22en-US%22%20mode%3D%22CREATE%22%3ERe%3A%20RT%201170%20Dual%20SDRAM%2016bit%20connection%3C%2FLINGO-SUB%3E%3CLINGO-BODY%20id%3D%22lingo-body-1986436%22%20slang%3D%22en-US%22%20mode%3D%22CREATE%22%3E%3CP%3EHi%26nbsp%3B%3CA%20href%3D%22https%3A%2F%2Fcommunity.nxp.com%2Ft5%2Fuser%2Fviewprofilepage%2Fuser-id%2F206069%22%20target%3D%22_blank%22%3E%40MaxM%3C%2FA%3E%2C%3C%2FP%3E%0A%3CP%3EUnfortunately%2C%20we%20do%20not%20have%20any%20reference%20schematics%20or%20benchmarks%20for%20a%20Dual%20SDRAM%20configuration%20on%20the%20RT1170%2C%20but%20I%20can%20say%20that%20you%20are%20definitely%20correct%20on%20the%20connection.%20All%20lines%20except%20CS0%20and%20CS1%20are%20connected%20in%20parallel%2C%20and%20the%20CS%20lines%20are%20connected%20to%20each%20of%20the%20SDRAMs.%3C%2FP%3E%0A%3CP%3EBR%2C%3CBR%20%2F%3EEdwin.%26nbsp%3B%3C%2FP%3E%3C%2FLINGO-BODY%3E