Proper way to set FlexSPI root clock

[derekkrouze]

Hello,

I am currently using an i.mx rt 1064 (528Mhz) and running a HyperRAM device off of FlexSPI1. I want to run the HyperRAM chip at 166Mhz which means I need to set the FlexSPI1 root clock to be 332Mhz, however this setting seems unreachable within the clock config tools. It is currently being driven off of these settings:

USB1 PLL: 480Mhz

PLL3_PFD0: 664.61Mhz (/13 * 18)

FLEXSPI_PODF: 2 (to get 332.3Mhz)

The clock config tools post an error saying that the FlexSPI root clock must be equal or lower to 332Mhz, however I am unable to find settings to get an even 332Mhz here. I can manually change the generated clock_config code to set the divider to 2 but modifying the generated code could pose an issue down the road if it were to be generated again. I could also copy the clock init code out of generated code but this presents an extra step as well. 

Is there a proper way to set the root clock to 332Mhz within the config tools?

[jeremyzhou]

Hi @derekkrouze ,
Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
1) Is there a proper way to set the root clock to 332Mhz within the config tools?
-- Actually, it's impossible to generate the perfect 332 MHz via the clock config tool, so I'd like to add the clock configuration code manually to make it, as below shows.

   CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll);
    CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 26);   /* Set PLL3 PFD0 clock 332MHZ. */
    CLOCK_SetMux(kCLOCK_FlexspiMux, 0x3); /* Choose PLL3 PFD0 clock as flexspi source clock. */
    CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0);   /* Divide the clock by 1 to get flexspi root clock 332MHZ */

Have a great day,
TIC

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