Peripheral access from both cores

[Mysterion]

Dear sirs,

does the i.MXRT117x allow access to any peripheral from both cores, or is the access limited to the peripherals each core is connected to directly?

In first case: is there any drawback, like slowing down the M7 AHB bus when accessing FlexSPI from the M4 core?

[Alexis_A · Accepted solution]

Hello @Mysterion,

Outside some GPIOs and the MMCAU there's not much restrictions about the peripherals. You can check this in the chapter 3.3.

About the performance, the FLEXIO limit frequency is independent from each core so the performance would only be affected in the data processing.

Best Regards,
Alexis Andalon