PMIC assert delay on LPM exit by wakeup interrupt

[pdgendt]

Hi,

Is it possible to delay the PMIC signal after wakeup PIN interrupt to exit suspended low power mode? Which registers should be set for this?

On the following image the controller goes into low power mode, and instantly the wakeup is triggered.

After 50us the PMIC signal turns back on, and as the 3v3 is still above 3V, the power-up sequence isn't respected and the controller ends up into a unrecoverable bricked state.

This is on a custom board, we did the same tests on the DEV board with the power toggle mode sample from MCUXPRESSO, which didn't brick.

Thanks in advance,

Pieter

[Simmatth]

Dear Omar

I'm a colleague of pdgendt and I read your explanation a couple of times. As we had major issues with the startup sequence of the controller, we thoroughly analised and tested our old and new circuits, which are based on the EVK.

While checking the schematic files of the MIMXRT1064-EVK, I noticed the UM805RE you are talking about is supervising the SNVS_3V3, not the main 3V3 voltage. In our own implementation we did the same, but of course as the 3V3 turns off when PMIC goes low, the SNVS remains stable at 3V3. Therefore the supervisor IC doesn't pull the DCDC_enable low when the PMIC is reasserted shortly after going into sleep mode.

Could you explain why this works on the EVK? What keeps the enable low after assertion of PMIC?

For now we fixed the issue by adding a delay circuit to the WAKEUP signal. This delays the interrupt (and thus the PMIC) until the DCDC_SWITCH is sufficiently discharged.

Kind regards
Simone

Ps.: I think you forgot to upload the image on you last reply!

[Omar_Anguiano]

Let me explain why this works on our EVK. 

In the EVK SNVS_3V3 is the same source as the main 3V3. Please refer to this picture on how this voltage monitor is implemented. 
So this monitor ensures PSWITCH is discharged when initializing the new power sequence. 

The solution of adding a delay circuit is also a suitable approach. 

Best regards,
Omar

[Omar_Anguiano · Accepted solution]

Hello

PMIC_ON_REQ signal cannot be delayed by sw as there 

We utilize voltage monitor circuit with delayed reset output (e.g. like UM805RE). This circuit monitors the main RT1xxx 3.3V power supply voltage (external 5V to 3.3V DCDC). When output voltage falls below a threshold (RE in device UM805) it generates reset signal (in our case it pulling reset output low) for specific delay (this delay must be considered enough to discharge capacitance across DCDC_PSWITCH, it means the voltage at DCDC_PSWITCH must go below 0.5V during this delay time). The reset output of this voltage monitor is connected to enable input of external DCDC, which means DCDC 3.3V output is disabled during whole reset delay interval. During this interval, it must be achieved that DCDC_PSWITCH will go below 0.5V. See the top-level picture below.

Best regards,
Omar