Max code size of RT1050 HAB Encrypted

キャンセル
次の結果を表示 
表示  限定  | 次の代わりに検索 
もしかして: 

Max code size of RT1050 HAB Encrypted

ソリューションへジャンプ
1,602件の閲覧回数
kensu
Contributor V

Hi

If I use RT1050 without SDRAM,

What is the max code size of "HAB Encrypted" mode?

In my understanding, the image must run on internal internal RAM or SDRAM for HAB Encrypted mode.

I read the "User Manual - MCUXpresso Secure Provisioning Tools".

For image running in internal RAM, it need move SRAM_ITC to first position.

My questions are:

1. Can "image running in internal RAM" only use the SRAM_ITC?

2. In this example, the max code side is 116K ?

3. Why shift 0x3000? 

pastedImage_1.png

Original memory location of SDK:

pastedImage_2.png

Regards

Ken

ラベル(1)
0 件の賞賛
返信
1 解決策
1,576件の閲覧回数
jeremyzhou
NXP Employee
NXP Employee
Hi,
Thank you for your interest in NXP Semiconductor products and
for the opportunity to serve you.
1) Can "image running in internal RAM" only use the SRAM_ITC?
-- No.
2) In this example, the max code side is 116K?
-- Yes.
3) Why shift 0x3000?
-- The 0x3000 is the offset of the application code in the SRAM_ITC after non-XIP boot successfully. This offset is not strict to 0x3000, it depends on the developer, usually, the offset is set to 0x2000.
Hope this is clear.
Have a great day,

TIC

 

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

 

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

元の投稿で解決策を見る

0 件の賞賛
返信
1 返信
1,577件の閲覧回数
jeremyzhou
NXP Employee
NXP Employee
Hi,
Thank you for your interest in NXP Semiconductor products and
for the opportunity to serve you.
1) Can "image running in internal RAM" only use the SRAM_ITC?
-- No.
2) In this example, the max code side is 116K?
-- Yes.
3) Why shift 0x3000?
-- The 0x3000 is the offset of the application code in the SRAM_ITC after non-XIP boot successfully. This offset is not strict to 0x3000, it depends on the developer, usually, the offset is set to 0x2000.
Hope this is clear.
Have a great day,

TIC

 

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

 

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------

0 件の賞賛
返信