Regarding this KB article:
https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Reallocating-the-FlexRAM/ta-p/1117649
I think there is a mistake in this, regarding the memory regions defined in BOARD_ConfigMPU() in board.c
The article says that region 5 is SRAM_ITC, region 6 is SRAM_DTC and region 7 is SRAM_OCRAM.
I think, region 4 is ITC (address 0), region 5 is DTC (address 20,000,000) and region 7 is OCRAM (address 20,280,000)
Does anyone else agree?
@mjbcswitzerland @victorjimenez @Sabina_Bruce
-Nick
Nick
There is no region that is fixed - each entry depends on how it is programmed by the code.
BOARD_ConfigMPU() will not be the same for each processor since the FlexRAM OCR address is not the same for an i.MX RT 1020 compared to an i.MX RT 1060, for example. Therefore it could decide to put the SRAM_ITC in region 1, 3 or 7, as it chooses, but the principle stays the same.
Regards
Mark
uTasker project developer for Kinetis and i.MX RT]
Contact me by personal message or on the uTasker web site to discuss professional training or product development requirements
Thanks both @mjbcswitzerland @victorjimenez
Yes now I can see that my board.c file contents (based on 1060) are different to the one that is used in the knowledge base (based on 1050).
But when you first read the knowledge base article, this is not obvious and is not made clear.
-Nick
Hi Nick,
Thanks for sharing your feedback! I will update the document to be more clear on this part!
Regards,
Victor
Hello Nick,
The regions mentioned in the community document are the correct ones. As you can see in the below image region 5 also starts at address 0x0 which corresponds to the ITC. Also, the size of this region matches the default FlexRAM configuration, 128KB, when the size of region 4 is 1GB. Region 4 does not correspond to the FlexRAM ITC.
Have a great day,
Victor
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