If `GPIO_SD_B1_05` is configured, a hardware fault occurs.

[kbsidi]

Running the following code in `pin_mux.c` causes a hardware fault.

...

IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_05_USDHC2_DATA1, 0U);

...

Operating environment

MCU : MIMXRT1024DAG5B

IDE
Product: MCUXpresso IDE
Version: MCUXpresso IDE v11.10.0 [Build 3148] [2024-07-03]
Operating system: Windows 10
VM: OpenJDK 64-Bit Server VM (64 bit)

SDK

[EdwinHz]

Hi @kbsidi,

This is because GPIO_SD_B1_05 is routed as the FlexSPI_DQS pin which, as mentioned on the EVK's schematic, needs to be floated for proper functionality of the QSPI Flash.

BR,
Edwin.

[kbsidi]

Then, should I use a different QSPI Flash RW speed instead of 133 MHz?
If so, how should I configure it?

[EdwinHz]

Hi @kbsidi,

I'm afraid this isn't possible. As mentioned on the Migration Guide from i.MX RT1020 to i.MX RT1024 (nxp.com): "RT1024 has only one FlexSPI port and is used for internal flash. RT1024 doesn’t support external FlexSPI flash, please use internal SIP flash instead." This means that the pins shown on "Table 3. i.MXRT1024 XIP boot option" are the only ones available for booting.

Sorry for the inconvenience this may cause.

BR,
Edwin.

[kbsidi]

Yes, I understand. I've also heard that reducing the Flash Clock speed to below 133 MHz might solve the issue.

[kbsidi]

I want to use both SD1 and SD2.