IMXRT1170 M4 run from FlexSPI alias

[radoslawp]

Hi. I have troubles running M4 code from FlexSPI aliased region (0x08000000). I am able to run it from "normal" region 0x30000000 but this region is not cached like the aliased one. Is there anything special about this region or it should be somehow enabled ?

[Masmiseim]

Hey @radoslawp,

There is actually nothing special about the alias address. You only have to reconfigure the linker accordingly in order to use the alias for the M4. Note, however, that the identical memory is referenced at 0x08000000 and 0x30000000. So if the M7 uses the first megabyte of the flash, the M4 may only use the memory from 0x08100000.
When the M4 is started by the M7, the start address in the 0x30000000 range must be passed to IOMUXC_LPSR_GPR->GPR0/1, not the alias range.
I have created an example with Coremark that implements this. See https://github.com/Masmiseim36/Coremark_iMXRT

By the way, the cache is also used on the M4 for the 0x30000000 range. However, the data cache is then also used for the instructions. The instruction cache is unused in this scenario.

Regards

[radoslawp]

Regarding cache that's why I want to use aliased Flash region so that I-CACHE and D-CACHE are utilized in the best possible scenario performance wise. From what I understood it means that although binary for M4 is built with aliased region addressing, the address put into GPR0/GPR1 must be non-aliased is that correct ? 

[Masmiseim]

Yes, the M7 is not aware of the alias addressing. That is M4 only.

[radoslawp]

Thanks for your reply, it was very informative. Maybe you will know the answer to the following question. We are using LPC-LINK2 as JLINK with segger tools and we are able to connect to M4 and stop it but while trying to setup a breakpoint it says that no hw breakpoints are available. Do you know the issue ? Is this JLink related or general issue with this processor ?

[Masmiseim]

Has your problem with the alias addresses on the M4 been solved?

Unfortunately, I can't say much about the breakpoint problem. The M4 has four hardware breakpoints; if these are already in use, a message like this may appear. Often one of these hardware breakpoints is reserved for single steps.

[radoslawp]

Actually I have resolved partially issue with Flash alias and also issue with breakpoints. This M4 uses FPBv1 which is able to set breakpoints only within 0x0-0x20000000 address space and it has 6 breakpoints (this is implementation dependent - you can read about it here https://developer.arm.com/documentation/ddi0403/d/Debug-Architecture/ARMv7-M-Debug/Flash-Patch-and-B... and check registers from debugger which I did). Therefore moving to 0x080000000 is not only good performance wise but also needed if you wanna actually debug it. I am still have some issues but moving towards the correct direction.

[Masmiseim]

Do you get the Breakpoint issue when you use Segger Ozone for Debugging?

[radoslawp]

I don't have this tool but as I found in IMXRT1170RM it is mentioned that "FPB for CM4 cannot be used since the flash address is beyond 0x20000000". Getting back to GPR0/GPR1 VTOR setting there can eb actually adress from 0x08000000 space set as that's exactly what NXP SDK example is doing. Nevertheless both solutions are working.

[mayliu1]

Hi @radoslawp ,

Thank you so much for your interest in our products and for using our community.

Please tell me your IDE,   is your project  CM7 core set master or MC4  coreset as master?

I suggest you can refer SDK demo 

\SDK_2_16_000_MIMXRT1170-EVKB\boards\evkmimxrt1170\multicore_examples\hello_world\cm7

\SDK_2_16_000_MIMXRT1170-EVKB\boards\evkmimxrt1170\multicore_examples\hello_world\cm4

Wish it helps you.
If you still have question about it, please kindly let me know.

Best Regards

mayliu

[radoslawp]

In NXP examples M4 is run from ITC RAM which is not the case for me. As I wrote I am able to run M4 (as slave) from "normal" flash region but not from "aliased" region.

[mayliu1]

Hi @radoslawp ,

Thanks for your reply.

I understand your needs, you want CM7 core as master, CM4 core as slave, both CM7 and CM4 are XIP .

Please refer  SDK demo as following.

\SDK_2_16_000_MIMXRT1170-EVKB\boards\evkmimxrt1170\demo_apps\hello_world_secondary_core_boot\cm7

\SDK_2_16_000_MIMXRT1170-EVKB\boards\evkmimxrt1170\demo_apps\hello_world_secondary_core_boot\cm4

The following image is shared by RT expert Jay on his blog.

Wish it helps you.
If you still have question about it, please kindly let me know.

Best  Regards

mayliu