Hi Dear Authorized,
I am a bit confused with your SRAM CLK Operations. Is there a verbal definitions related to SYNC Mode and ASYNC Mode for SRAM Operations (Read/Write).
As I know in normal literature; ASYNC mode is clock signal independent operations and SYNC is vice versa of it. However, SRAM operations in both SYNC and ASYNC uses a clock as we see in the reference manual below. Therefore I am not able to decide which one to be used. Could you please help me ? If is there specific document related to SRAM Operations. I will be glad for sharing it with me.
Why ASYNC Write/Read operations uses semc_clk ?
Why SYNC Write/Read operations uses CLK ?
Why Register Access uses ipg_clk ?
Thanks and Regards.
Hi Lukas,
Why ASYNC Write/Read operations uses semc_clk ?
TS: There is a Note below Figure 25-59. ASYNC SRAM Read in ADMUX Address Mode with below info:
semc_clk and rxclkn are the internal signals. semc_clk is the SEMC functional clock. rxclkn is the clock to sample data from SRAM.
semc_clk signal does not connect with external SRAM device, only using within RT1064 SEMC module.
The ASYNC figure provided semc_clk signal to clearly show how many clock cycle for each operation.
Why SYNC Write/Read operations uses CLK ?
TS: CLK signal is the real clock line connects with external SRAM device.
Why Register Access uses ipg_clk ?
TS: I think it was a document issue, should be semc_clk. From Table 14-4, there shows SEMC only has one module clock: semc_clk.
best regards,
Mike
Hi Lukas,
Why ASYNC Write/Read operations uses semc_clk ?
TS: There is a Note below Figure 25-59. ASYNC SRAM Read in ADMUX Address Mode with below info:
semc_clk and rxclkn are the internal signals. semc_clk is the SEMC functional clock. rxclkn is the clock to sample data from SRAM.
semc_clk signal does not connect with external SRAM device, only using within RT1064 SEMC module.
The ASYNC figure provided semc_clk signal to clearly show how many clock cycle for each operation.
Why SYNC Write/Read operations uses CLK ?
TS: CLK signal is the real clock line connects with external SRAM device.
Why Register Access uses ipg_clk ?
TS: I think it was a document issue, should be semc_clk. From Table 14-4, there shows SEMC only has one module clock: semc_clk.
best regards,
Mike
