I.MX R1170 SEMC SDRAM interrupt during SRAM access

[Eugene3]

Hi 
I'm connecting SDRAM(CS0) and SRAM(CSX1) to the SEMC of RT1170.
I found CS0 sometimes had low pulse while CSX1 was low, which means SEMC had an interrupt access to SDRAM while SEMC was accessing SRAM.
Is it possible to prevent SDRAM access while accessing SRAM?

[Omar_Anguiano]

I believe that the interruption of SDRAM is due to the auto-refresh command, so adjusting the timing of SDRAM refresh is crucial to prevent this.
Also implementing different settings on the BMRC registers might be helpful, I suggest the setting of 0x81 to prevent re-ordering of the commands.

Best regards,
Omar

[Eugene3]

Hi @Omar_Anguiano 

>>adjusting the timing of SDRAM refresh is crucial to prevent this.

I'm using Auto Refresh so, I tried to adjust SDRAMCR3[31-1], for example changed to UT = RT or UT < RT.  However the result was same, there are still interruption of SDRAM.

How can I avoid the interruption?  BMCR are set to 0x81.

[Omar_Anguiano]

Which specific command of the SDRAM is interrumping the SRAM access? 
The goal of having BMCR to 0x81 is to avoid re-ordering of the command queue so the commands are executed under "first in first out" policy. 

UT and RT are suggested to stay the same, changing them to the highest refresh period possible by the memory might reduce the interruption of SDRAM as I suspect that the interruption is the auto-refresh command. 

Best regards,
Omar

[Eugene3]

Hi @Omar_Anguiano 

>>Which specific command of the SDRAM is interrumping the SRAM access? 

I checked the interruption and it was "Precharge All Banks" and "Auto Refresh". 

Is it possible to prevent these SDRAM interruptions? Which setting is causing this behavior?

[Omar_Anguiano]

The SEMC sends PRECHARGE ALL command to close any opened page on device before sending AUTO REFRESH command. So if the Auto-refresh is disable then both commands will not be executed. This is disabled on SDRAMCR3[REN] field. 
Please consider that if refresh is not done with the sdram timings it may cause loosing some data on the sdram. 

Best regards,
Omar

[Eugene3]

Hi @Omar_Anguiano 

Thank you for your support.

Do you mean it's impossible to prevent SDRAM refresh from interrupting SRAM access while Auto-Refresh is enabled?

Do you have any sample projects where the Auto-Refresh is disabled?

[Omar_Anguiano]

Yes as auto-refresh is executed periodically. Unfortuantely, we don't have an example of this specific implementation. 

Best regards,
Omar

[Eugene3]

Hi @Omar_Anguiano 

I found other related thread.

In this thread, NXP described ">>1. The SDRAM refresh command is inserted between SEMC burst access.".

It looks I can prevent SDRAM refresh from interrupting SRAM access while Auto-Refresh is enabled.

Which is correct?

https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Questions-when-using-SDRAM-and-SRAM-together-on-...

[Omar_Anguiano · Accepted solution]

Yes, the auto-refresh still interrupts the burts operation if necesary to execute refresh. It just splits the burst so it can insert auto-refresh in between. 

Best regards,
Omar

[Eugene3]

Hi

Thank you for your information.

But how can I adjust the timing of SDRAM refresh? Should I change UT[31-24] value? 

Currently I set UT[31-24] and RT[23-16] on SDRAMCR3 as same value because NXP recommended. 

BMRC registers are 0x81.