How to distinguish received CAN frame format(CNA2.0B or CAN FD) for RT1060

[HM_UoP]

According to the processor reference of IMXRT, we can know that FLEXCANFD module supports both CAN2.0B and CAN FD protocol.

This means that after FLEXCANFD is initialized to CANFD mode, it can allow sending/receiving both CAN2.0B format frames and CAN FD format frames as required. 

The actual test results are also in line with expectations, although there is a tiny bug in FLEXCAN_WriteFDTxMb function that needs to be fixed (CAN_CS_EDL(1)  should be CAN_CS_EDL(pTxFrame->edl)) .

The result of my test is that FLEXCANFD can also receive CAN messages in CAN2.0B and CANFD frame formats at the same time. But I can't use flexcan_fd_frame_t.edl to distinguish which format the received frame is. The flexcan_fd_frame_t.edl is always 0 regardless of whether the received message is a 2.0B frame or an FD frame.

Does anyone have any suggestions? Thank you.

[HM_UoP · Accepted solution]

I have figured out the issue, which is also due to the bug of fsl_flexcan.c

Adding the following code to the function FLEXCAN_ReadFDRxMb can fix the issue.

....

/* Get the Extended Data Length. */
pRxFrame->edl = (uint8_t)((cs_temp & CAN_CS_EDL_MASK) >> CAN_CS_EDL_SHIFT);

/* Get the Error State Indicator */
pRxFrame->esi = (uint8_t)((cs_temp & CAN_CS_ESI_MASK) >> CAN_CS_ESI_SHIFT);

/* Get the Substitute Remote Request */
pRxFrame->srr = (uint8_t)((cs_temp & CAN_CS_SRR_MASK) >> CAN_CS_SRR_SHIFT);

/* Get the Bit Rate Switch */
pRxFrame->brs = (uint8_t)((cs_temp & CAN_CS_BRS_MASK) >> CAN_CS_BRS_SHIFT);

...

[guys_fr]

Ho yes, there is two table

Table 44-4. Message Buffer Structure

Table 45-26. Message buffer structure — example with 64-byte payload

[guys_fr]

Is the EDL bit set even if payload is less or equal to 8 ?, would make sens and give FD ind bit.

[HM_UoP]

@guys_fr Yes, the EDL bit indicates if the CAN frame is a CANFD frame or a CAN2.0B frame. The CAN FD frame can also have less than 8 bytes of payload.

[guys_fr]

I am confused

S32K 53.4.3 Message buffer structure have a 4 bits fields but 2 bits in the structure. What is the code says ?

[guys_fr]

misleading, there is 4 bits, 27-24

[guys_fr]

Yes there is four combination, the Message Buffer Structure doesn't have FD indication bit. Unclear about Rx FIFO with an 8 bytes payload compatibility mode in FD, would be nice!