GPIO interrupt high/low level sensitive interrupt clearing

[houe]

I am using an IMXRT1020 MCU.

I have configured a GPIO interrupt to be "high-level sensitive" in the ICR1 register.

The documentation for the ISR register states:

"When the active condition has been detected, the corresponding bit remains set until cleared by software. Status flags are cleared by writing a 1 to the corresponding bit position."

However, I am seeing the ISR bit clear automatically when the GPIO level goes low. That is I am not having to write a 1 to clear the interrupt status flag.

I have tested this when the GPIO interrupt is set to "rising-edge sensitive" and indeed I do have to clear the ISR bit by writing a 1 to it in that case.

Question: Why do I not have to clear the ISR bit in software for the "high-level sensitive" interrupt? Is this correct behavior? Is the documentation incorrect?

Thanks.

[jay_heng]

Interesting finding, let me reproduce it on my side and get back to you.

[houe]

Any updates on being able to reproduce?

[jay_heng]

I can reproduce it on my side. and yes it is different from Kinetis but same as LPC.

GPIO level interrupt is not commonly used in application. what kind of scene you want to use it?

[houe]

First, currently I do no have a software problem per say - the code works fine (see below). I just observed this behavior and could not find anything in the reference manual documenting this is how it should operate so I was a little concerned. Seems that this is correct behavior but is not mentioned in the reference manual (or did I miss it?). It would be nice to update the documentation if its not currently there. Could save others having to go down this same road...

Thank you for confirming this - much appreciated.

Now to my use case...

Yes, agreed level interrupt is not commonly used. My particular use case is a secondary processor lets the host (IMXRT1020) know when data is to be read. It does this by setting a host interrupt pin high. The line remains high so long as there are messages to read. Once the last message is read the line goes low.

The IMXRT level interrupt queues up the reading of a single message and then we disable the interrupt. Once the single message is read the interrupt is reenabled and if more messages are available the interrupt will fire again (since host interrupt line is still high). This sequence continues until the line goes low. The code works fine.

[jay_heng]

Your use case make sense. and I have written one blog to descript NXP MCU level interrupt behavior in detail. FYI. yes, i will let the doc team update RM

https://www.cnblogs.com/henjay724/p/16999794.html