GPIO edge-detect minimum pulse width

[gavin5342]

My question is similar to https://community.nxp.com/t5/i-MX-RT/MIMXRT1051-What-is-the-minimum-asynchronous-input-pulse-width/t... but, unfortunately, the answer isn't posted.  I would like to know the minimum pulse width to trigger the edge-detect logic described in section 12.3.2 Interrupt Control Unit of the IMXRT1050RM (user manual).

My use case is that an FPGA will send a pulse on a state transition which I use to interrupt the processor.  It seemed to work OK at 10ns, but on some later hardware that hasn't been so reliable.

Is there any more information you can give on the operation of the edge-detect circuit?

[gavin5342]

Hello Leo,

Sorry that I was not clear.  I have a pulse which signals an event and I want to use a falling edge detect interrupt to catch it.  I don't want to measure the pulse width.

The specification that you highlighted is the maximum transition time, but that does not define how long the pulse needs to be for it to trigger the interrupt.  The transition time on my signal is much shorter than the maximum (mine is around 0.7ns).

If you don't have a specification, could you tell me how the edge-detect works?  Is it a digital circuit that might change with clock frequency, or is it implemented using a delay line?

[_Leo_]

Hi,

Thank you so much for your interest in our products and for using our community.

I must admit that I a little bit confused with "GPIO edge-detect minimum pulse width". If you want to configure a input interrupt to be rising/falling edge, the spec is the following:

But if you want to measure the pulse width of a signal it is convenient to do with the input capture with a timer, and in this case is typically limited by the clock frequency of the timer that you use.

Have a nice day!