How can I change the bytes per frame in the flexio spi example for IMX RT1060? I need to send 96 byes in a single transfer. Is that even possible?
Thank you!
Hi Mike,
I tried using your code on my iMX RT1062, but I had no success. I attached a copy of my source code. I can see only the first byte is sent. Could you please have a look?
You mentioned before that the buffer is only 32 bits, and I am still not sure how you managed to send 64 bits in a single frame.
Cheers!
Hi Andre,
Could you debug the code?
If yes, please set a breakpoint at FLEXIO_SPI_WriteData() function entry point in FLEXIO_SPI_MasterTransferNonBlocking() function. Then you could see if the FLEXIO_SPI_WriteData() will be called twice or more times.
I did the quick test, I just using the fixed data in FLEXIO_SPI_WriteData() function:
You could set the TRANSFER_SIZE be 8 for a quick check.
Thanks for the attention.
best regards,
Mike
Could you please share your code or just the changes you had to make to the driver?
Thank you Mike.
Thank you Mike!
Hi Andre,
Thanks for the patience.
I do the test with one frame with 32bit with MSB (total transfer size is 8 bytes), and directly write 32bit value to Shiftbuffer with FLEXIO_SPI_WriteData() function in <fsl_flexio_spi.h> file :
I could get below SPI transfer signal:
If I send data 0x87654321, I would get below transfer signal:
I did another test with SPI frame size to 64bit with MSB:
I don't change the code to write 64bit data at the same time, which need software support to write the Shift buffer register (32bit) twice with different value. During the test, it will write the Shiftbuffer twice with same value 0x87654321. Then I could get below transfer signal with 64bit
I did the test for 32bit LSB to send 8bytes with value 0x8765432187654321, get below transfer signal:
I did the test for 64bit LSB to send 8bytes with value 0x8765432187654321, get below transfer signal:
Above is my test results for your reference.
Customer do need to change the FlexIO for SPI driver to suitable related modification.
Wish it helps.
best regards,
Mike
Thank you mike and Sebastian!
Yes, it would be great if mike can show if he can send 64 bits on Mosi line in a single frame. Can you send this value for example:0x1234567887654321, and show it on the scope please.
I was able to generate 64 clock cycles as you did, but the challenge is in data transmit on the Mosi.
cheers!
Hi Andre,
I will do related test this Friday and let you all know the result.
Thanks for the patience.
best regards,
Mike
Hi Mike,
im trying to overcome this buffer side limitation by sending two sets of data: 32 bits each, but the issue is that there is a time delay of 1.5 clock cycle between each 32 bits transfer. Is there anyway to make this delay zero?
Thanks,
Hi Andre,
I made below modification with <fsl_flexio_spi.c> FLEXIO_SPI_MasterTransferNonBlocking() function and related _flexio_spi_transfer_flags in <fsl_flexio_spi.h>:
/* Configure the values in handle */
switch (xfer->flags)
{
case kFLEXIO_SPI_8bitMsb:
dataMode = (8 * 2 - 1U) << 8U;
handle->bytePerFrame = 1U;
handle->direction = kFLEXIO_SPI_MsbFirst;
break;
case kFLEXIO_SPI_8bitLsb:
dataMode = (8 * 2 - 1U) << 8U;
handle->bytePerFrame = 1U;
handle->direction = kFLEXIO_SPI_LsbFirst;
break;
case kFLEXIO_SPI_16bitMsb:
dataMode = (16 * 2 - 1U) << 8U;
handle->bytePerFrame = 2U;
handle->direction = kFLEXIO_SPI_MsbFirst;
break;
case kFLEXIO_SPI_16bitLsb:
dataMode = (16 * 2 - 1U) << 8U;
handle->bytePerFrame = 2U;
handle->direction = kFLEXIO_SPI_LsbFirst;
break;
case kFLEXIO_SPI_32bitMsb:
dataMode = (32 * 2 - 1U) << 8U;
handle->bytePerFrame = 4U;
handle->direction = kFLEXIO_SPI_MsbFirst;
break;
case kFLEXIO_SPI_64bitMsb:
dataMode = (64 * 2 - 1U) << 8U;
handle->bytePerFrame = 8U;
handle->direction = kFLEXIO_SPI_MsbFirst;
break;
default:
dataMode = (8 * 2 - 1U) << 8U;
handle->bytePerFrame = 1U;
handle->direction = kFLEXIO_SPI_MsbFirst;
assert(true);
break;
}
/*! @brief Define FlexIO SPI transfer flags. */
enum _flexio_spi_transfer_flags
{
kFLEXIO_SPI_8bitMsb = 0x1U, /*!< FlexIO SPI 8-bit MSB first */
kFLEXIO_SPI_8bitLsb = 0x2U, /*!< FlexIO SPI 8-bit LSB first */
kFLEXIO_SPI_16bitMsb = 0x9U, /*!< FlexIO SPI 16-bit MSB first */
kFLEXIO_SPI_16bitLsb = 0xaU, /*!< FlexIO SPI 16-bit LSB first */
kFLEXIO_SPI_32bitMsb = 0xbU,
kFLEXIO_SPI_64bitMsb = 0xcU,
};
During the master transfer using related setting:
/*Start master transfer*/
masterXfer.txData = masterTxData;
masterXfer.rxData = masterRxData;
masterXfer.dataSize = TRANSFER_SIZE;
masterXfer.flags = kFLEXIO_SPI_32bitMsb;
Then I could get below SPI communication signals:
If I use kFLEXIO_SPI_64bitMsb, then I could get below SPI communication signals:
Wish it helps.
Have a great day,
Mike
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Hi Mike,
if I understand Andre correctly I am having the exact same problem. To my understanding, Andre wants to have a seamless frame of more than 32 bit at the MOSI pin. But in the figures you showed, the MOSI is constant so I don’t understand if your approach solves the problem or not.
Additionally, I don’t know how to implement your solution. In particular I don't have the files <fsl_flexio_spi.c> and <fsl_flexio_spi.h>. I am using S32 Design Studio for ARM which provides <flexion_spi_driver.c> in which the non-blocking master transfer function is named FLEXIO_SPI_DRV_MasterTransfer(). How can I implement sending long seamless frames on this basis?
Thanks a lot for your help
Sebastian
Farid
I was able to generate a flexio Spi clock of 1khz by changing the source clock of the flexio peripheral. Now I generated 48 clock cycles that I need for my single transfer of 6 bytes. The issue I’m having now is I can’t send all of my 6 bytes in a single data frame. What settings do I need to change to be able to send more than 2 bytes. In the driver I only see options for sending 16 bits of data. Do I need to modify the driver, if so please give me some guidelines.
Thank you!
Hi Andre,
Sorry for the delay reply.
There do need to modify the SDK provided driver.
While, I don't find there with combined shifter description for shifter data output with RT1060 FlexIO module.
The SHIFTBUF size is 32bit, which doesn't support up to 6 bytes transfer in a single data frame.
Sorry for that.
Have a great day,
Mike
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Please, any comments on my question above?
Thank you!’
Hi,
would it be possible to generate a Flexio SPI clock of 1KHz? if so can you say how this can be done on the flexio spi example in the SDK. I tried to use to config tool and it tells me 1KHz is out of range. i need to this low clock just to clock a stream of data that I am sending to another device.
Regards,
Is it possible to change the number of bytes per frame to 96 bytes instead of 2 byte in the structure you mentioned? I need a transfer of 96 bytes in a single transfer, with no gaps in between bytes.
Thanks
Hi,
I checked with RT product team, the RT1060 FlexIO shifter number is 4, each shifter supports 4 bytes.
If all 4 shifters using for SPI TX, which could support up to 16 bytes per frame.
If it still need supporting SPI TX&RX, which could support up to 8 bytes per frame.
There is impossible to set 96 bytes in a single frame.
Thanks for the attention.
best regards,
Mike
Hi,
The FlexIO SPI master handle structure definition the SPI mode of how many bytes in a Frame.
There only with two types: one byte or two bytes in a frame.
Customer could refer SDK provided [evkmimxrt1060_flexio_spi_int_lpspi_transfer_master] demo to set the TRANSFER_SIZE value to transfer 96bytes with call FlexIO spi transfer API function once.
Wish it helps.
Have a great day,
Mike
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