FlexIO Parallel Transmit for DAC

[aberger]

I am working with the IMXRT1050-EVKB. I am hoping to implement a parallel interface for transmitting samples to a 16-bit DAC on a 10 MHz sample clock. I think the FlexIO peripheral should be able to handle this. Unfortunately none of the examples in the SDK_2.x_EVKB-IMXRT1050 demonstrate parallel transmit with the FlexIO.

I need to setup something like:

1. A timer module that serves as (1) the FlexIO trigger, (2) an ISR trigger, and (3) has an associated output pin to serve as the DAC data CLK. I'm unsure whether to use PIT, QTIMER,  or FlexPWM for this). 

2. In the ISR, the DAC output is calculated and placed into a DMA buffer (for the FlexIO Shift Buffer).

3. The FlexIO module shifts data from the DMA buffer onto the 16 output pins as triggered by the timer module. The triggered FlexIO timer must be configured so that the the parallel output pins are driven with appropriate Data Setup and Data Hold time relative to the CLK pin associated with the timer module. (Or maybe the CLK pin should be driven by the FlexIO timer itself? I'm unsure).

It would be great if I could test this with the IMXRT1050-EVKB board, but there aren't many options for accessing the FlexIO pins. I could use J35 (the 24-pin FFC connector for the camera module), which provides ~14 digital pins. This would allow me to simulate a 12 or 13-bit parallel interface + CLK line. 

Can you recommend a starting point for this application?

[aberger]

I was able to get FlexIO working for 16-bit parallel updates. While my goal was to perform updates at 10 MHz, I could only get it to reliably work up to 6 MHz. I believe the limitation is the IPG_CLK that runs the DMA transfers (for further discussion, see the README.md in the attached project). 

To answer the above question comparing FlexIO vs DMA and GPIO: In comparison to using a QTIMER module with DMA and GPIO, FlexIO is able to perform parallel data output updates 2x faster. For discussion of the implementation of 16-bit parallel output with QTIMER, DMA, and GPIO see https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Trigger-DMA-write-with-TMR-CMPLD1/m-p/2137698/hi.... (Here I was able to clock out 16-bit updates at up to 3 MHz. The limitation there is that two DMA transfers must occur... one to update the QTIMER CMPLD register, and a linked channel to perform the DMA update to the GPIO pins. With FlexIO, only the DMA transfer to the FlexIO shiftbuffer needs to occur with each DMA request... hence the update rate improvement of 2x). 

Any comments or suggestions are welcome. I hope someone else finds this example code for implementing a parallel interface over FlexIO useful.

[aberger]

What are the advantages to using FlexIO for this application, as compared to DMA and GPIO (plus a QTIMER module, to trigger the DMA transfers, and provide a DAC Clock with a precising timing relationship to the DMA transfers)?

[MultipleMonomials]

> Or maybe the CLK pin should be driven by the FlexIO timer itself? I'm unsure

Yes! To generate a clock signal, you should route the timer's Output to a pin.

P.S. I posted some other info in a thread here that might be useful for general FlexIO development: https://community.nxp.com/t5/i-MX-RT-Crossover-MCUs/Continuous-pin-read-using-FlexIO/m-p/1977331

[aberger]

I could use J35 (the 24-pin FFC connector for the camera module), which provides ~14 digital pins

On further investigation, it looks like the FlexIO pins on the demo board are all used up by LCDIF, ENET, and SEMC. So I would be better off connecting to J8, the 40 pin LCD connector.