I am working on evaluating/implementing different options to attach
external hardware to the RT1020 for our future product. Currently I try
to find out how much performance loss is incurred when using a PSRAM for
parts of the program's data instead of the internal SRAM/DTC when the
PSRAM is attached via (quad) SPI. I have the basic communication
working, have set up my own LUT according to the datasheet and the
correct AHB indices etc. I can read and write from the PSRAM via
direct/AHB memory accesses.
However, one major obstacle in actually using it came up during
testing. My current understanding is that the PSRAM wraps around if a
transfer crosses a 1024 bytes page boundary. This is an issue if
prefetching is enabled because this causes reads that cross these
boundaries if the start address of the read is within the last N-1
bytes for prefetching blocks of size N. In that case the read partially
returns wrong data towards the end of the read (i.e., the data located
at the beginning of the page where the read started instead of the
following page). I can send you pictures of the signal trace or other
additional information if anything is unclear.
Since I cannot limit the start addresses of the reads, FLEXSPI has to
deal with this to allow for enabling prefetching. I have tried
understanding as much of the FLEXSPI configuration as possible by
cross-referencing TRMs from multiple members of the RT family, the ANs
I am working on evaluating/implementing different options to attach
external hardware to the RT1020 for our future product. Currently I try
to find out how much performance loss is incurred when using a PSRAM for
parts of the program's data instead of the internal SRAM/DTC when the
PSRAM is attached via (quad) SPI. I have the basic communication
working, have set up my own LUT according to the datasheet and the
correct AHB indices etc. I can read and write from the PSRAM via
direct/AHB memory accesses.
However, one major obstacle in actually using it came up during
testing. My current understanding is that the PSRAM wraps around if a
transfer crosses a 1024 bytes page boundary. This is an issue if
prefetching is enabled because this causes reads that cross these
boundaries if the start address of the read is within the last N-1
bytes for prefetching blocks of size N. In that case the read partially
returns wrong data towards the end of the read (i.e., the data located
at the beginning of the page where the read started instead of the
following page). I can send you pictures of the signal trace or other
additional information if anything is unclear.
Since I cannot limit the start addresses of the reads, FLEXSPI has to
deal with this to allow for enabling prefetching. I have tried
understanding as much of the FLEXSPI configuration as possible by
cross-referencing TRMs from multiple members of the RT family, the ANs
on related topics such as 12239, 12437, 13028 and also the insightful
blog posts by @jay_heng (e.g.,
https://www.cnblogs.com/henjay724/p/14742519.html) but to no avail. The
only thing that came up during my research is the ALIGNMENT field of
AHBCR described in RT1020 RM that looks like it might be intended to
solve this problem. Unfortunately, I could not find any more
information than the one sentence in the register description and some
preliminary testing of setting the respective bits didn't show any
effect.
I am looking for any additional information or insights on how to confine the
AHB-incurred reads to the PSRAM's page boundaries? Thanks!
