Ethernet SMI MDC Polarity Incorrect

[nmeltzer]

Hello,

Short Description

Data on the MDIO pin (from the IMXRT1064 to SMSC LAN9303) changes on the rising edge of the clock (MDC pin). This is inconsistent with what the IMX1064 reference manual says, as well as with the way the SMI bus is defined. 

I am wondering if there is a way to change the clock polarity.

Detailed Description

We have hardware which must support ethernet. We just moved from a single-port phy to a 3-port network switch, the chip is the SMSC LAN9303.

Before we changed, ethernet was functioning well. I believe this was due to the external phy being more forgiving on the SMI bus protocol.

When we switched, the ethernet phy no longer responded to the default mcux ethernet driver that we were using, despite supporting the same 803.11 SMI commands.

Upon closer investigation, we found that the signals coming from the MDC and MDIO pins did not look correct.

What we observed

The SMSC LAN9303 defines it's SMI frame format over MDIO/MDC in the following diagram:

The LAN9303 byte test registers, 0x064 and 0x065, are supposed to read out words that, together, read '0x87654321'.

Here is a capture of that transaction:

Initially, the command (first 16 bits) looks correct, even if the data read from the PHY does not.

The command word are generated directly from the IMXRT1064, and so is the MDC signal.

Upon closer inspection, however, it can be seen that the MDIO signal changes on the rising edge of the MDC signal:

Section 41.3.17.1 in the IMXRT1064 reference manual contradicts this behavior:

Additionally, the SMSC9303 manual says that MDIO data is sampled on the rising edge of the MDC signal.

Both of these documents say that data it latched on the rising edge of MDC.

As far as I can tell, there is no way to change the clock polarity of MDC. This behavior is independent of the phy, since the commands are generated by the IMXRT.

I am wondering if anyone can help figure out what we might be missing.

Platform

MCU: MIMXRT1064CVL5B

3-Port Switch: SMSC LAN9303

RTOS: ZephyrOS

Thank you for your time,

Noah

[nmeltzer]

Hello again,

I want to provide more information:

We reloaded the firmware onto the old hardware (where the ethernet works properly), and we took a look at the MDC and MDIO pins on that board.

We noticed the same issue, where the MDC signal coming out of the IMX had the wrong polarity. When looking at the signal, we found that the phy was also not responding to the IMXRT on the 'working' hardware either. The reason the old hardware worked was because the phy was strapped properly, and it was enough to make ethernet work with no MDIO/MDC communication.

[nmeltzer]

We worked around this by using the I2C interface on the PHY instead of the the MDC/MDIO pins. 

This does, still seem to be an issue; even outside of my group.

In order to replicated this, use an NXP IMXRT1064 eval kit and try to read any of the registers using the MDC/MDIO bus. For example, read the PHY_ID_LSB and PHY_ID_MSB to see if you get the correct data back.

[diego_charles]

Hi @nmeltzer 

Thank you for your patience and your update. 

As I understand  that you are seeing an error on the polarity of the MDIO pin, and you had to communicate with your ethernet switch over I2C, as a workarround. Also, I understand that you where able to see the same behaviour when running your new SW on our EVK. 

I want to replicate this issue. But could you help me with the steps?

1. - Get RT1064 EVK ( which uses the  KSZ8081 phy )
2. -Get latest SDK version ( or which version did you used?)
3. -Pick a demo where the Board PHY gets interfaced and   the  PHY_KSZ8081_Init() SDK funtion is implemented. 
4. - Check on which MDC edge of the MDIO signal changes. (  From fsl_phy.h, which defines PHY registers according to IEEE802.3, which registers map to the  PHY_ID_LSB and PHY_ID_MSB  ones you are mentioning? Or could I see this when reading other registers?)

 Thank you for your help. 

Diego