EVK IMXRT1176 SDRAM(heap and data usage with DCD) and NAND Flash

[ahmedhrabi]

Hello, 

Can someone tell me if it is possible to use the SDRAM and the NAND Flash simultaneously on the EVK IMXRT1176 as below: 

• SDRAM initialized with DCD
• Heap section resides in the SDRAM
• NAND flash initialized in main with SEMC and used to store some data.

I tried to do that on the SDK project "evkmimxrt1170_nand_flash_management_cm7" by moving heap  to SDRAM but Nand Flash read operation crash when trying to malloc memory (SDK_Malloc).

Regards.

[application_ninja]

Hello all, was this ever resolved? I am attempting the exact same scenario, except on the EVKB board, and would like to know if a solution was ever found, an example project would be great!

[application_ninja]

Hello NXP, anything?

[Omar_Anguiano]

Hello
I Hope you are well.

It is possible to have multiple memories in your application but they need to accessed at different times. You cannot use SDRAM while NAND is being used.

Additionally, if SDRAM is used to execute code it is important to make sure that NAND is not used while the code is being executed.

If you have more questions do not hesitate to ask me.
Best regards,
Omar

[ahmedhrabi]

Hello @Omar_Anguiano , 

Thanks for your reply. Well i just inhibited the semc_init function and it works fine. 

My application is executed on Qspi Flash with XIP and SDRAM is used to place heap as mentioned in the main question.

Well i'm facing another problem that is easy to reproduce : 

Placing Stack and global data on SDRAM are making troubles. (However placing only heap on sdram works as charm). 

Here is the steps to reproduce the problem: 

• In the SDK project "evkmimxrt1170_nand_flash_management_cm7" i added the flag XIP_BOOT_HEADER_DCD_ENABLE=1 for using DCD init for SDRAM.
• I commented the line that reinitialize semc (SEMC_Init(SEMC, &config);) for not losing SDRAM ROM config.
• I placed Stack heap and global data on SDRAM : 
• And then all the application goes wrong. 

As i mentioned below adding only heap to sdram works for me.

Regards.

[Omar_Anguiano]

Thank you for your additional information.
To place these sections on SDRAM it is needed to make sure that SDRAM is enabled at first, you can do this with DCD. Also, it is needed to disable the cache: heap and the stack on the SDRAM on MIMXRT1064 Eval... - NXP Community

Best regards,
Omar

[ahmedhrabi]

That do not seems to have any effect the problem is always here.

Regards.

[Omar_Anguiano]

Checking this it seems that when using the NAND in the SEMC SDRAM enters a conflict. When you try to add stack and heap to SDRAM to a project which do not uses SEMC is the issue still present?

Best regards,
Omar

[ahmedhrabi]

@Omar_Anguiano, 

No when i try to add stack and heap to SDRAM to a project which do not uses SEMC there is no issues.

Regards.

[Omar_Anguiano]

Thank you!
Please add a higher priority to the SDRAM access through the BMCRx registers.
This is used to balance external memory access efficiency, urgency, and latency based on your requirements.

Best regards,
Omar

[ahmedhrabi]

Thank you for you reply,

Can you please give more informations about how to give the SDRAM higher priority.

Actually my BMCRx (0 and 1) registers are configured with 0x81 value.

I don't see how to set a Queue A or B priority in function of the support access (SDRAM, NAND Flash or other). 

There's just the Score of the Queue that gives more or less priority to the operations but that don't depend on the access area am i right?

Regards,

HRABI.

[Omar_Anguiano]

You're correct. Recommend to set BMCR0/1 with 0x0 for applications that require restrict sequence of transactions, such as stack is allocated in SDRAM. The write and read transactions to the same address might be reordered if transactions in the queue is reordered, and it might crash the routine. WQOS can be non-zero value if needed, meanwhile WAGE must be non-zero value. WRWS and WSH should be 0x0.

Best regards,
Omar