Does the IMXRT1020 Reference Manual show false information to the SRC_SRSR tempsense_rst_b bit?

[imxrtuser]

Hello,

in the text to 20.8.3 SRC Reset Status Register SRC_SRSR is written that the register is write one to clear.

The graphical view of the register

shows that bit 0 to 7 are write one to clear but the tempsense_rst_b is not.

Is the picture or is the text not correct?

Kind regards,

Stefan

[jeremyzhou]

Hi  Stefan Mitterhauser ,

Thank you for your interest in NXP Semiconductor products and
for the opportunity to serve you.
1) Is the picture or is the text not correct?
-- No, it's correct.

Have a great day,
TIC

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[imxrtuser · Accepted solution]

Hi Jeremy,

thank you for your reply. I figured out that the tempsense_rst_b is not write one to clear so the figure is correct. It is not the complete register write one to clear.

Kind regards,

Stefan

[jeremyzhou]

Hi  Stefan Mitterhauser ,

Thanks for your reply and I was wondering if you can upload your demo code and introduce the testing procedure, as I'd like to verify it by myself prior to reporting.

Have a great day,
TIC

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[imxrtuser]

Hi Jeremy,

I realized that there is an example project src_reset_source and the driver fsl_src.c. I only verified that the driver function SRC_ClearResetStatusFlags() does clear the tempsense_rst_b bit by writing zero to it and not by writing one.

Kind regards,

Stefan

[jeremyzhou]

Hi  Stefan Mitterhauser ,

Thanks for your reply and I've verified it.
The text information about the SRC Reset Status Register SRC_SRSR needs to be corrected to keep consistent with the figure and SRC_ClearResetStatusFlags() function.

Have a great day,
TIC

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