DMA error in Channel 81

[oayastuy]

Hello everyone,

I'm using DMA to perform readings from ADC_ETC, and it's working correctly.

So far, I've been using a PWM trigger to start the conversion, and at the end of the ADC_ETC chain, it generates a DMA request on channel 64: ADC_ETC.

Now, I want to use 2 PWM triggers to perform two different chains and have them generate two DMA requests on two different channels.

As a first step, I've linked COCO0 to DMA channel 81 using XBAR, and in DMA0, I simply modified the transfer channel from 64 to 81. However, this didn't work.

While debugging (by routing COCO0 to a pin), I've noticed that a 40ms pulse is generated correctly, leading me to believe that the issue lies within the DMA. What could be happening? Even when generating pulses manually on DMA channel 81, no transfer is performed.

Best regards,

iMXRT1170 

[RaRo]

Hello @oayastuy,

Just for double check, could you please verify you are linking COCO0 to XBAR1_OUT0 as DMA request on channel 81 responds to XBAR1_OUT0?

[i.MX RT1170 Processor Reference Manual. Chapter 4. Interrupts, DMA Events, and XBAR Assignments. Table 4-3. DMA Mux Mapping]

On RT1170 for configure the XBAR1_OUT0 please refer to i.MX RT1170 Processor Reference Manual. Chapter 83. Inter-Peripheral Crossbar Switch A (XBARA). There, could you please verify your configuration of XBARAx_SEL0 and XBARAx_CTRL0 registers?

XBARAx_CTRL0 register needs to be configured to enable the DMA for XBAR_OUT0 in bit 0 [DEN0].

Best regards, Raul.

[oayastuy]

Hi Raul,

I checked what you say with the following results:

• COCO0 is linked to XBAR1_OUT0
  • Code:
    

    

  • XBARAx_SEL0 Register value :

• DMA is enabled for OUT0:
  • Code:

    

  • XBARAx_CTRL0 registers DEN0 bit value:

Still, even though it works with the ADC_ETC channel (channel 64), I can't get it to work with the XBAR1_OUT00 channel (channel 81).

Best regards, Odei.

[RaRo · Accepted solution]

Hello @oayastuy,

Could you please try using the RT1170 EVKB SDK's xbara_cm7 example to use channel 81? The example uses kXBARA1_OutputDmaChMuxReq81 with PIT interruption, but could be useful to see how the channel 81 is being configured.

Also, if possible, could you please share your XBARA configuration for further analysis?

Best regards, Raul.

[oayastuy]

Hello Raul,

Thank you for your response. I have successfully resolved the problem by following the provided example.

The resulting code is as follows:

    /* Init xbara module. */
    XBARA_Init(XBARA1);

    /* Link the ADC_ETC trigger signals from PWM*/
    XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputFlexpwm1Pwm0OutTrig0, kXBARA1_OutputAdcEtc0Coco0);
    XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputFlexpwm1Pwm0OutTrig1, kXBARA1_OutputAdcEtc0Coco1);

    /* Link the ADC_COCO signal to DMA */
    XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputAdcEtc0Coco0, kXBARA1_OutputDmaChMuxReq81);
    XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputAdcEtc1Coco0, kXBARA1_OutputDmaChMuxReq82);

    /* Configure the XBARA DMA. */
    xbaraConfig1.activeEdge  = kXBARA_EdgeRising;
    xbaraConfig1.requestType = kXBARA_RequestDMAEnable;
    XBARA_SetOutputSignalConfig(XBARA1, kXBARA1_OutputDmaChMuxReq81, &xbaraConfig1);

    xbaraConfig2.activeEdge  = kXBARA_EdgeRising;
    xbaraConfig2.requestType = kXBARA_RequestDMAEnable;
    XBARA_SetOutputSignalConfig(XBARA1, kXBARA1_OutputDmaChMuxReq82, &xbaraConfig2);

Best regards,

Odei