I would like to connect iMX RT1024 to MR5A16A MRAM
MR5A16A MRAM datasheet states it is compatibile with SRAM interface
However by comparing waveforms in both MR5A16A datasheet and iMX RT1024 reference manual I found one issue with iMX RT1024 SRAM operations.
MR5A16A MRAM states that address lines must be valid at the time when Chip Enable goes low
iMX RT1024 Reference Manual states that Chip Enable goes low before address is valid and CE# setup time can not be 0.
Is there a way to properly connect these chips?
Also I was looking at many SRAM chips and all of them need Address to be valid at the time when Chip Enable goes low. This raises the question of whether iMX RT1024 waveforms are valid and how should proper communication with SRAM look like.
