In EMC tests, fifth and sixth harmonics radiated emissions are over the limit. The reason seems to be SEMC clk, whose frequency is about 164Mhz. Thus we would like to reduce SDRAM clock frequency.
We are using SDRAM for data, so we have defined SKIP_SYSCLK_INIT and XIP_BOOT_HEADER_DCD_ENABLE=1. If we change the SEMC clk frequency with clock tool, it has no effect due to the definition SKIP_SYSCLK_INIT. How can we change the SEMC clk frequency? Is it possible (and how) to configure SEMC signals (clk, data...) via SW?
In the imxrt64 EVK, there is a 0 Ohm resistor in clk signal line. Is it possible to lower the rise time of clock pulse by increasing the resistor value? In oscilloscope measurement, the clock signal looked like a synthetic sine wave. Is that correct, or due to too low bandwidth of the oscilloscope?
