Hi, we have a custom board using an RT1020 connected to an SDRAM. The SDRAM is specifically the ISSI IS42S81600F-7TL. We ran the SDK example called "evkmimxrt1020_semc". The example was successfully executed with no error in all tests. We modified the values of the semc_sdram_config_t struct used to setting up the parameters for SEMC. We used the following values according to SDRAM datasheet.
status_t BOARD_InitSEMC(void)
{
semc_config_t config;
semc_sdram_config_t sdramconfig;
uint32_t clockFrq = EXAMPLE_SEMC_CLK_FREQ;
/* Initializes the MAC configure structure to zero. */
memset(&config, 0, sizeof(semc_config_t));
memset(&sdramconfig, 0, sizeof(semc_sdram_config_t));
/* Initialize SEMC. */
SEMC_GetDefaultConfig(&config);
config.dqsMode = kSEMC_Loopbackdqspad; /* For more accurate timing. */
SEMC_Init(SEMC, &config);
/* Configure SDRAM. */
sdramconfig.csxPinMux = kSEMC_MUXCSX0;
sdramconfig.address = 0x80000000;
sdramconfig.memsize_kbytes = 16 * 1024; /* 16MB = 16*1024*1KBytes*/
sdramconfig.portSize = kSEMC_PortSize8Bit;
sdramconfig.burstLen = kSEMC_Sdram_BurstLen1;
sdramconfig.columnAddrBitNum = kSEMC_SdramColunm_10bit;
sdramconfig.casLatency = kSEMC_LatencyTwo;
sdramconfig.tPrecharge2Act_Ns = 15; /* Trp 15ns */
sdramconfig.tAct2ReadWrite_Ns = 15; /* Trcd 15ns */
sdramconfig.tRefreshRecovery_Ns = 67; /* Use the maximum of the (Trfc , Txsr). */
sdramconfig.tWriteRecovery_Ns = 12; /* 12ns */
sdramconfig.tCkeOff_Ns =
42; /* The minimum cycle of SDRAM CLK off state. CKE is off in self refresh at a minimum period tRAS.*/
sdramconfig.tAct2Prechage_Ns = 37; /* Tras 37 */
sdramconfig.tSelfRefRecovery_Ns = 67;
sdramconfig.tRefresh2Refresh_Ns = 60;
sdramconfig.tAct2Act_Ns = 60;
sdramconfig.tPrescalePeriod_Ns = 160 * (1000000000 / clockFrq);
sdramconfig.refreshPeriod_nsPerRow = 64 * 1000000 / 8192; /* 64ms/8192 */
sdramconfig.refreshUrgThreshold = sdramconfig.refreshPeriod_nsPerRow;
sdramconfig.refreshBurstLen = 1;
return SEMC_ConfigureSDRAM(SEMC, kSEMC_SDRAM_CS0, &sdramconfig, clockFrq);
}
The SDRAM seems to work OK at this point. Then, when we want to create a DCD for the ROM to initialize the SDRAM to use it as main memory (stack + heap + .data + .bss) we get a Hard Fault on startup (before main function). I attached the DCD we used. The following screenshot is the point before a Hard Fault is triggered
Using the "Memory" window when we write the value 0x11223344 at address 0x80_000_000 and initialize the SEMC inside the main function in ""evkmimxrt1020_semc"" example we see that it is written correctly.
When we do the same using DCD configuration we can clearly see that it is not written correctly. (Look at adress 0x80_000_000 in memory window)
We have reviewed the DCD over and over again. Is there anything we are not considering?
Our problem seems to be to build a DCD according to the configuration we used in the example.
