SDK_2_12_1_MIMXRT1064xxxxA fsl_clock.c
In the function CLOCK_GetSysPfdFreq(clock_pfd_t pfd) when CLOCK_GetPllFreq() returns the frequency of the Bypass Reference Clock, the returned frequency is divided by the pfd clock divider and multiplied by 18U. For the bypass clock, this should not occur.
uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd)
{
uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllSys);
switch (pfd)
{
case kCLOCK_Pfd0:
freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT);
break;
case kCLOCK_Pfd1:
freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT);
break;
case kCLOCK_Pfd2:
freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT);
break;
case kCLOCK_Pfd3:
freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT);
break;
default:
freq = 0U;
break;
}
freq *= 18U;
return freq;
}
Clock tool reference example:
