Boot i.mxrt1051 from alternate QSPI pins

[eamonnheffernan]

Hi, for pin reasons, I'd like to use the alternate/secondary pins for QSPI, connecting to GPIO_AD_B1_xx instead of the primary GPIO_SD_B1_xx pins. Before I commit to a pcb, I have some questions, and I would appreciate any helpful advice.

1. Will the 1051 reliably boot from the alternate pinset? There is no hint given to the device via BOOT_CFG pins to tell it to use the alternate pinset. Does it just test both pinsets, and use whichever one has a flash attached?

2. Does NXP have a schematic for such a configuration? Or a description of how to connect the QSPI to the 1051? (EVKB, Arch Mix, SOMLab Vision boards all use the primary pinset.) Table 11, Page 15 of MIMXRT105060HDUG.pdf provides a list of pins. Is this what I should use?

3. What should I do with FLEXSPI_A_DQS? Mux it out and let it float?

4. Table 3 of AN12108 gives a list of supported QSPI devices. Is this list valid for the alternate pinset too?

5. Can I flash and debug normally with the alternate pinset? (I'm using a Link2 debugger.)

6. Is there any performance difference between the two pinset choices.

7. Any gotchas that I should be aware of?

Ok, a lot of questions, but I would be very grateful if anyone out there who has used the alternate pinset could help me with these questions. I really don't want to print a pcb and then find it just doesn't work.

Thanks so much

Eamonn

[eamonnheffernan]

Victor, thank you for your detailed answer. This is very helpful.

Best regards - Eamonn

[eamonnheffernan]

After trawling through many posts here, and further dives into the RM and App Notes, I have found answers to some of my questions.

1. BOOT_CFG2[2:0] = 111b will select QSPI on secondary pinmux, 3B SPI mode.

    BOOT_CFG1[7:0] should be either 0x02or 0x00 depending on whether your image is encrypted XIP or not (0x00).

2. Schematic: Haven't found one yet.

3. DQS: Don't know yet.

4. Devices: https://community.nxp.com/thread/509297  suggests ISSI IS25LP064A works, but Cypress S25FL256S not.

5. Flash+Debug: Don't know yet. (I'm using Lpc-Link2 and McuXpresso.)

6. Don't know yet.

7. Gotchas: seems we need external pullups on /HOLD pin

"About the pull up, some QSPI flash internal have the pull up, but it's better in HOLD and WP pin add external 4.7K pull up resistor to make sure the QSPI flash work." (from QSPI Initial loading on secondary pinmux ).

Thanks to people for posting their experiences. It is very helpful.

I'll continue looking into my remaining questions.

Eamonn

[victorjimenez · Accepted solution]

Hello Eamonn, 

2. Does NXP have a schematic for such a configuration? Or a description of how to connect the QSPI to the 1051? (EVKB, Arch Mix, SOMLab Vision boards all use the primary pinset.) Table 11, Page 15 of MIMXRT105060HDUG.pdf provides a list of pins. Is this what I should use?

The RT1050-EVKB comes with an Hyperflash and a QSPI. By default the RT boots from the Hyperflash, however, you can make some changes to boot from the QSPI instead. The following application note explains how to achieve this: https://www.nxp.com/docs/en/application-note/AN12108.pdf. 

Unfortunately, we don't have any schematic that uses the alternate QSPI pins. 

3. What should I do with FLEXSPI_A_DQS? Mux it out and let it float?

SPI interface requires CS pin, not DQS. DQS pin is not an essential feature of Flash memory. So, it is not shown in Flash connection diagram of figure 27-3 in iMXRT1050 reference manual section 27.5.3. Although DQS need be provided in some external DRAM/HyperRAM IC’s as such in S26KS256SDPBHV020.  

5. Can I flash and debug normally with the alternate pinset? (I'm using a Link2 debugger.)

Yes, you shouldn't face any problems if you boot from the alternate pins. 

6. Is there any performance difference between the two pinset choices.

No. 

Have a great day,

Victor

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