About RT1052 Read flash and D-cache

[gossipboy]

All,

    RT1052 Enable Dcache and write spiflash will leads to hardfault "bus fault" sometimes.I don't know what happens.So Whats the solution about R/W spiflash and enable dcache at the same times?

    Note:I have to use emwin. So the codes download into the flash but running in the sdram.MAYBE everytime Write flash I have to disable flash?

[jeremyzhou]

Hi,
Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
1) MAYBE everytime Write flash I have to disable flash?
-- No, however, you need to maintain the cache ache data coherency problem in another way.
So I'd like to suggest you to refer the flexspi_nor_polling_transfer demo in the SDK library.
TIC

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[gossipboy]

Thanks for your support.

I read the demo again you suggest,I find a code "SCB_DisableDCache();" before the demo operate flash,so I think when the demo write flash ,the Dcache has been disabled.

[gossipboy]

sorry,disable dcache