All,
RT1052 Enable Dcache and write spiflash will leads to hardfault "bus fault" sometimes.I don't know what happens.So Whats the solution about R/W spiflash and enable dcache at the same times?
Note:I have to use emwin. So the codes download into the flash but running in the sdram.MAYBE everytime Write flash I have to disable flash?
Hi,
Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
1) MAYBE everytime Write flash I have to disable flash?
-- No, however, you need to maintain the cache ache data coherency problem in another way.
So I'd like to suggest you to refer the flexspi_nor_polling_transfer demo in the SDK library.
TIC
-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!
- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------
Thanks for your support.
I read the demo again you suggest,I find a code "SCB_DisableDCache();" before the demo operate flash,so I think when the demo write flash ,the Dcache has been disabled.
sorry,disable dcache