RT1170 flexSPI1 secondary QSPI flash debug flashdriver
1. Abstract
RT1170 has two groups of flexSPI: FlexSPI1, FlexSPI2. Each group of flexSPI is also divided into primary option group and secondary pin group. For specific chip connections, please refer to the following article:
https://www.cnblogs.com/henjay724/p/15139381.html
NXP provided burning algorithms are started from the flexSPI1 primary group for RT1170. However, in actual use, some customers need to start from the flash of the FlexSPI1 secondary pin group and use the debugger to program the chip. How to prepare the corresponding flash algorithm? Moreover, different debuggers correspond to different program algorithms.
This article will take RT1170 flexSPI1 secondary pin group flash boot as an example to explain how to use CMSIS DAP and JLINK as debugger to prepare the corresponding burning algorithm and do debug, as well as the necessary conditions for booting from the secondary port, and provide modified flash algorithm which can be directly used to debug and programming.
Here, I would like to thank the customer who are providing the test platform, because the official MIMXRT1170-EVK is an external QSPI flash connected from the FlexSPI1 primary interface and does not provide a secondary group interface.
2 Related prepare
To test the FlexSPI1 Secondary pin group, you must first prepare a board that connects the QSPI flash to the Secondary pin, and then configure the FlexSPI_PIN_GROUP_SEL fuse to 1. Since the FlexSPI1 secondary pin group is already connected to the GPIO_AD port, the maximum speed limit is 104Mhz.
Fig 1
2.1 Hardware prepare
Fig 2
2.2 fuse FLEXSPI_PIN_GROUP_SEL burn
FLEXSPI_PIN_GROUP_SEL fuse address is 0X9A0[10]:
Fig 3
To burn fuse, let the chip to enter serial download mode and connect through MCUBootutility. When connecting, you need to select the FlexSPI1 secondary option, as follows:
Fig 4
Burn fuse result is:
Fig 5
After the fuse is burned successfully, change the board boot mode to internal boot mode, then we can program the app and boot from the flash which is connecting to the FlexSPI1 secondary pin group.
3 Flash algorithm modification and debug test
Regarding the flash algorithm of RT1170 FlexSPI1 for secondary pin group, this article mainly focuses on the preparation and testing of MCUxpresso IDE, two debuggers: CMSIS DAP's .cfx, and JLINK's RT-UFL flash algorithm.
Here is a brief explanation of the principle of modifying the flash algorithm. It is actually based on the ROM API. Therefore, the main modification point is :
option0 =0xc1000005, option1=0x00010000.
Fig 6
3.1 CMSIS DAP .cfx flash algorithm prepare and test
The algorithm source code of RT1170 CMSIS DAP can be found in the path of MCUXpressoIDE:
C:\nxp\MCUXpressoIDE_11.8.0_1165\ide\Examples\Flashdrivers\NXP\iMXRT\iMXRT117x_FlexSPI_SFDP.zip
To the new MCUXpresso IDE 11.10, use this path:
C:\NXP\MCUXpressoIDE_11.10.0_3148\ide\LinkServer\Examples\Flashdrivers\NXP\iMXRT\iMXRT117x_FlexSPI_SFDP.zip
After importing the algorithm source code, first compile the LPCXFlashDriverLib<Release_SectorHashing> version to get the lib that needs to be called. For iMXRTt117x_FlexSPI_SFDP, select the MIMXRT1170_SFDP_QSPI (FlexSPI1 Port A QSPI) version, and modify Imxrt117xFlexSPI_SFDP, FlashConfig.h:
#define CONFIG_OPTION0 0xc1 000005
#define CONFIG_OPTION1 0x00010000
Then compile the lib and compile Imxrt117xFlexSPI_SFDP to generate .cfx,
Fig 7
After build, the .cfx file can be found in project folder:
iMXRT117x_FlexSPI_SFDP\builds
Rename it: MIMXRT1170_SFDP_QSPI1_Secondary.cfx, and copy it to the IDE installation directory:
C:\nxp\MCUXpressoIDE_11.8.0_1165\ide\binaries\Flash
This is done for the later app, you can directly select the corresponding .cfx in the list.
For details on how to compile the algorithm source code to obtain .cfx, you can refer to the article:
https://www.cnblogs.com/henjay724/p/14190485.html
After preparing the APP and CMSIS DAP debugger, select compiled .cfx flash algorithm in the app project:
Fig 8
To the app, it should be noted that the serialClkFreq in the FCB is configured as 100MHz, and the LUT commander matches the flash command used. The FCB of W25Q128 is as follows:
const flexspi_nor_config_t qspiflash_config = {
.memConfig =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.readSampleClksrc=kFlexSPIReadSampleClk_LoopbackFromDqsPad,
.csHoldTime = 3u,
.csSetupTime = 3u,
// Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
.controllerMiscOption = 0x10,
.deviceType = kFlexSpiDeviceType_SerialNOR,
.sflashPadType = kSerialFlash_4Pads,
.serialClkFreq = kFlexSpiSerialClk_100MHz,//kFlexSpiSerialClk_133MHz,
.sflashA1Size = 16u * 1024u * 1024u,
.lookupTable =
{
// Read LUTs
[0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEC, RADDR_SDR, FLEXSPI_4PAD, 0x20),
[1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
// Read Status LUTs
[4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),
// Write Enable LUTs
[4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x0),
// Erase Sector LUTs
[4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x21, RADDR_SDR, FLEXSPI_1PAD, 0x20),
// Erase Block LUTs
[4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18),
// Pape Program LUTs
[4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x12, RADDR_SDR, FLEXSPI_1PAD, 0x20),
[4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),
// Erase Chip LUTs
[4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0x0),
},
},
.pageSize = 256u,
.sectorSize = 4u * 1024u,
.ipcmdSerialClkFreq = 0x1,
.blockSize = 64u * 1024u,
.isUniformBlockSize = false,
};
Debug result is:
Fig 9
It can be seen that the modified flexSPI1 secondary group flash algorithm has been successfully called, the downloading is successful, and the app function runs normally.
3.2 JLINK RT-UFL flash algorithm prepare and test
Some customers like to use JLINK, but the Segger JLINK driver algorithm source code are not open, so you can use the RT-UFL algorithm, modify it to match the option of RT1170 FlexSPI1 secondray group, and then call it.
For information on the RT-UFL algorithm, please see the following link:
https://www.cnblogs.com/henjay724/p/13951686.html
https://www.cnblogs.com/henjay724/p/14942574.html
https://www.cnblogs.com/henjay724/p/15430619.html
To the RT UFL modification points: ufl_main.c
case kChipId_RT116x:
case kChipId_RT117x:
uflTargetDesc->flexspiInstance = MIMXRT117X_1st_FLEXSPI_INSTANCE;
uflTargetDesc->flexspiBaseAddr = MIMXRT117X_1st_FLEXSPI_BASE;
uflTargetDesc->flashBaseAddr = MIMXRT117X_1st_FLEXSPI_AMBA_BASE;
uflTargetDesc->configOption.option0.U = 0xc1000005;
uflTargetDesc->configOption.option1.U = 0x00010000;
Build the code, generate: MIMXRT_FLEXSPI_UV5_UFL_Flexspi1secondary_qspi.FLM，copy
To:
C:\Program Files\SEGGER\JLINKV768B\Devices\NXP\iMXRT_UFL
Please note, to the SEGGER DRIVER path, it determined by your own JLINK driver version install path.
In file C:\Program Files\SEGGER\JLINKV768B\JLinkDevices.xml, add the new flash algorithm file calling code:
<!------------------------>
<Device>
<ChipInfo Vendor="NXP"
Name="MIMXRT1170_UFL_flexspi1_2nd"
WorkRAMAddr="0x20240000"
WorkRAMSize="0x00040000"
Core="JLINK_CORE_CORTEX_M7"
JLinkScriptFile="Devices/NXP/iMXRT_UFL/iMXRT117x_CortexM7.JLinkScript"
Aliases="MIMXRT1176xxx8_M7; MIMXRT1176xxxA_M7" />
<FlashBankInfo Name="QSPI Flash"
BaseAddr="0x30000000"
MaxSize="0x01000000"
Loader="Devices/NXP/iMXRT_UFL/MIMXRT_FLEXSPI_UV5_UFL_Flexspi1secondary_qspi.FLM"
LoaderType="FLASH_ALGO_TYPE_OPEN" />
</Device>
<!------------------------>
In the app project, debug configuration，configure the JLINK device as:
MIMXRT1170_UFL_flexspi1_2nd
Note: uncheck “reset before running”, otherwise, it will be stopped in ROM after entering the debug mode.
Fig 10
Test the debug result is:
Fig 11
We can see, when use the modified RT-UFL, the JLINK debug also works OK.
4. summarize
This article mainly provides the algorithm modification of RT1170 FlexSPI1 secondary group. The algorithm modification of other Flash interfaces and port is similar. The main attention is paid to fuse and algorithm matching. This article provides two modified FlexSPI1 secondary group burning algorithms: MIMXRT1170_SFDP_QSPI1_Secondary.cfx
RT-UFL modified MIMXRT_FLEXSPI_UV5_UFL_Flexspi1secondary_qspi.FLM
attachments:
CMSIS DAP：
RT117X FlexSPI1 2nd flashalgo->CMSIS DAP->MIMXRT1170_SFDP_QSPI1_Secondary.cfx
JLINK RT-UFL：
RT117X FlexSPI1 2nd flashalgo\JLINK RT-UFL
Copy JLINK RT-UFL folder to Segger JLINK install path:
C:\Program Files\SEGGER\JLINKV768B
In this way, the relevant flash algorithm can be called according to the above content.
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