where is the clk pin for pcie port on i.mx6q?

[gaoweilin]

hello everyone!

    I want to use the pcie port of i.mx6q to communicate with a endporint device,  but in the reference design of sarbelite，I didn't find  pcie clk, only the tx and rx data lane included in  the design. I wonder how to connect the clk pins in my own sch .Any suggestion would be appreciated!

    Regards!

   Weilin Gao

[EricNelson]

Hello Gaoweilin,

The SABRE Lite doesn't generate the PCIe clock from the i.MX6 because the PCIe was a late addition to the design.

Instead, there's an on-board oscillator on the PCIe daughter board:
     http://boundarydevices.com/product/nit6x_pcie/

You should follow richard.zhu's advice and refer to the SABRE SD or ARD designs for this but to generate the clock on the i.MX6.

[richard_zhu]

In general, the usage of the CLK in PCIe world has three models:

* Only PCIe RC has its own CLK resource, and routed out ref_clk to PCIe EP.

* PCIe RC/EP use the same CLK resource as the ref_clk.

* PCIe EP/RC has their own standalone PCIe CLK resource.

Up to now, option1 is used in  imx6 SD/ARD boards PCIe HW design.

[richard_zhu]

Please make a reference to the schematic of imx6 SD/ARD boards.

CLK1_N/P would be used to provided the CLK to PCIe EP device in the imx6 SD/ARD boards PCIe design.

[AnsonHuang]

Hi, Weilin

     On our SabreSD board, we use CLK1_N and CLK1_P to output clk to the endpoint device. And you can config our anatop module to output the clk to your endpoint.

     For more detail info, please refer to our PCIe driver and owner.

[乐乐季]

Hi yongcai :

my board is sabrelite,I According to the sabresd for chang my board-mx6q_sabrelite.c.

That is:

/************************************************************************************************/

1.static const struct imx_pcie_platform_data mx6_sabrelite_pcie_data __initconst = {

      .pcie_pwr_en = -EINVAL,

      .pcie_rst = SABRELITE_PCIE_RST_B_REVB,

      .pcie_wake_up = SABRELITE_PCIE_WAKE_B,

      .pcie_dis = -EINVAL,]

     #ifdef CONFIG_IMX_PCIE_EP_MODE_IN_EP_RC_SYS

     .type_ep = 1,

    #else

    .type_ep = 0,

    #endif

};

2. I add "imx6q_add_pcie(&mx6_sabrelite_pcie_data);" in mx6_sabrelite_board_init;

3. System Type  --->Freescale MXC Implementations  --->[*] PCI Express support (no RC and EP)

    Bus support  --->  PCI Express support

/***********************************************************************************************/

but my pcie clock not out,and I use the CLK1_N/CLK_P for the pcie clock.

please!