where is IMX6Q's PCIE_CLK signal?

[翔李]

hi,

where is IMX6Q's PCIE_CLK signal? I can find the PCIE_RXM/RXP and PCIE_TXM/TXP,but there is no REFCLK_M/REFCLK_P? can the PCIE device work where the IMX6Q don't output the clock to it?

Again,i find CLK1_P CLK1_N,CLK2_P CLK2_N in the pin C7 D7,C5 D5 of IMX6Q,so can i use CLK1 or CLK2 to feed the PCIE+_CLK input pin of the PCIE device,for example, TW6869?

[Yuri · Accepted solution]

  HW Design Checking List for i.Mx6DQSDL Rev2.7 conatins useful recommendations :

"Due to CLKx_P/N is LVDS port and don't match with PCIe reference clock specification.

For PCIe Gen1 application, following low cost soultion can be used(DC bias and AC

impedance should be considered).  Please refer to "HW Design Checking List for i.Mx6DQSDL

Rev2.7.xlsx", sheet "Schematic", Ref12 for more info."

"PCIe reference clock solution which provided by CLKx_N/P of i.MX6 chip can't pass PCIe

Gen2 compliance test.  Recommend using external PCIe 2.0/3.0 clock generator with 2 HCSL

outputs solution. One clock channel connect to i.MX6 as a reference input, please click

Ref14 ("HW Design Checking List for i.Mx6DQSDL Rev2.7.xlsx") for reference circuit.

Another clock channel should connect to PCIe connector, please contact generator vendor

for detailed design guide."

HW Design Checking List for i.MX6DQSDL

Regards,

Yuri.

[翔李]

hi,

thanks a lot.

I find a ref sch of IMX6Q,look at p.16 i.MX6  SABRE_AI_DESIGNFILES schematic SPF-27142_d_x4.pdf,there is two ways for the PCIEV2.0 clk,one is using Y1-AUDIO OSC and U12-pi90lv179,another is using Y4-100M OSC to PCIE device.so, ican use anyone of the two?

Q:

1:why do Y1-24.7456MHZ OSC directly connect to ESAI_SSI_EXT1_CLK(CLK2)?the LCK2_PN already connects to ESAI_SSI_EXT1_CLK(CLK2).

2: what's the meaning of"Oscillator module needed because MX6 on-chip audio clock source not routed out CLK2_N/P" at pAGE 7 SABRE_AI_DESIGNFILES schematic SPF-27142_d_x4 ?

[igorpadykov]

You can add necessary external 100MHz oscillator instead Y1 and use options

populating and not populating R590,R589,R583,R582 and

provide necessary signals to CLK2 and external mini-PCIe connector.

regarding Q1 and 2 I think they are already answered.

[igorpadykov]

Hi 翔 李

yes CLK1 or CLK2 can be used for outputting PCIe clk signal,

please look at p.16 i.MX6 Sabre schematic SPF-27392

i.MX6_SABRE_SDP_DESIGNFILES

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

[翔李]

HI,

there is a problem when i use pcie v2.0 VERSION.

there is another reply i following:

Re: where is IMX6Q's PCIE_CLK signal?

Yuri 2014-10-31 上午3:28 （回复 翔 李）

  HW Design Checking List for i.Mx6DQSDL Rev2.7 conatins useful recommendations :

"Due to CLKx_P/N is LVDS port and don't match with PCIe reference clock specification.

For PCIe Gen1 application, following low cost soultion can be used(DC bias and AC

impedance should be considered).  Please refer to "HW Design Checking List for i.Mx6DQSDL

Rev2.7.xlsx", sheet "Schematic", Ref12 for more info."

"PCIe reference clock solution which provided by CLKx_N/P of i.MX6 chip can't pass PCIe

Gen2 compliance test.  Recommend using external PCIe 2.0/3.0 clock generator with 2 HCSL

outputs solution. One clock channel connect to i.MX6 as a reference input, please click

Ref14 ("HW Design Checking List for i.Mx6DQSDL Rev2.7.xlsx") for reference circuit.

Another clock channel should connect to PCIe connector, please contact generator vendor

for detailed design guide."

HW Design Checking List for i.MX6DQSDL

so,please check it,thanks.

and,

I find a ref sch of IMX6Q,look at p.16 i.MX6  SABRE_AI_DESIGNFILES schematic SPF-27142_d_x4.pdf,there is two ways for the PCIEV2.0 clk,one is using Y1-AUDIO OSC and U12-pi90lv179,another is using Y4-100M OSC to PCIE device.so, ican use anyone of the two?

Q:

1:why do Y1-24.7456MHZ OSC directly connect to ESAI_SSI_EXT1_CLK(CLK2)?the LCK2_PN already connects to ESAI_SSI_EXT1_CLK(CLK2).

2: what's the meaning of"Oscillator module needed because MX6 on-chip audio clock source not routed out CLK2_N/P" at pAGE 7 SABRE_AI_DESIGNFILES schematic SPF-27142_d_x4 ?

[igorpadykov]

regarding "there is a problem when i use pcie v2.0 VERSION"

I totally do not understand your comments sorry.

Y1-24.7456MHZ OSC directly connect to ESAI_SSI_EXT1_CLK

for providing external option to clock to ESAI - to connector and to processor.

[igorpadykov]

yes, one can use both options

1. CLK2 pair can be used also for ESAI module, not only for PCIe

2. external oscillator is used for EASI clock provided to P1B coonnectot on p.20

[翔李]

hi，

i don't use ESAI module,but only pcie.so,i can delete the Y1-AUDIO OSC and U12-pi90lv179,also delete the Y4-100M OSC.

but i want to support the PCIE2.0 device,do i need add a external  PCIe 2.0/3.0 clock generator with 2 HCSL,One clock channel connect to i.MX6 as a reference input, Another clock channel should connect to PCIe connector?

At pAGE13 SABRE_AI_DESIGNFILES schematic SPF-27142_d_x4 ,there is a note"Circuit board passed PCIe 2.5G compliance test", is it mean this circuit is ok for PCIE1.0? and the pcie2.0 is 5Gbps.

[igorpadykov]

you can use all possible options.

Actually not all PCIe cards use reference clock.

>is it mean this circuit is ok for PCIE1.0? and the pcie2.0 is 5Gbps.

Yes.