Ed
We are sorry for getting back to you so late. For some reason that the answer was not put in right place. I paste it here. Hopefully it is useful.
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Is likely reserving the MMU L1 cache memory region parameters Non cacheable, sherable and RW access are typicall properties for a region memory that in this case MMU can access.
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If it is a good answer, we are going to close the discussion in 3 days. If you still need help, please feel free to reply with an update to this discussion.
Thanks,
Yixing