what is the latency between HW interrupt and ISR function in i.MX8mm

[imx8-mdt]

Hello experts,

I am running bsp L5.4.24 on i.MX8MM EVK.

I config the GPIO5_13 as a normal GPIO input pin.

and use 

devm_request_irq(gpio_dev->dev, gpio_dev->irq, cosmo_gpio_uart_recv_irq,IRQF_TRIGGER_FALLING,"irqname", NULL)  to prepare the ISR.

In cosmo_gpio_uart_recv_irq(), only record the irq count.

static irqreturn_t cosmo_gpio_uart_recv_irq(int irq, void *dev_id)
{
   irq_counts++;
  return IRQ_HANDLED;

}

I found if the GPIO5_13 triggers a very frequent  falling_edge (for example, total 5 falling_edge, 200us between two falling_edge) ,

The ISR will miss 2 interrupt , the  irq_counts is only 3.

if I pull another GPIO to measure it with oscilloscope as below:

int bb=0;
static irqreturn_t cosmo_gpio_uart_recv_irq(int irq, void *dev_id)
{
    irq_counts++;
   gpiod_set_value(gpio_dev->gpiod2,bb);
   bb=!bb;
  return IRQ_HANDLED;

}

in oscilloscope ,it shows the latency between real hardware interrupt and gpiod_set_value() is about 380us.

380 microseconds is the expected value?

How can I optimize to decrease the latency?

I hope to record the counts of square wave whose period time is 200us in this pin.

Thanks

[Dhruvit]

Hi @imx8-mdt,

I hope you are doing well

There is not any information for a particular value of the interrupt latency as multiple processes are running on the Linux and the interrupt will be taken care of as per its priority.

To decrease the latency, one can try with the cortex M core.

Also setting the higher priority for the interrupt may improve the latency.

For the information related to interrupt latencies on M cores, one can look at AN12078  Measuring Interrupt Latency.

For IMX6, please find below the available information for the same. 

https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Interrupt-latency-in-i-MX6SLX-M4-with-MQ...

Thanks & Regards,

Dhruvit Vasavada