weird IPU DP register macro define on kernel 3.0.35

[wallyyeh]

Hi, guys:

    recently I found kernel 3.0.35 had different IPU DP register macros  with kernel 3.10.17:

in kernel/drivers/mxc/ipu3/ipu_regs.h:

3.0.35:

#define DP_SYNC 0

#define DP_ASYNC0 0x60

#define DP_ASYNC1 0xBC

#define DP_COM_CONF(flow)    (flow/4)

#define DP_GRAPH_WIND_CTRL(flow) (0x0004/4 + flow/4)

#define DP_FG_POS(flow)        (0x0008/4 + flow/4)

#define DP_CUR_POS(flow)        (0x000C/4 + flow/4)

#define DP_CUR_MAP(flow)        (0x0010/4 + flow/4)

#define DP_GAMMA_C(flow, i)    (0x0014/4 + flow/4 + i)

#define DP_GAMMA_S(flow, i)    (0x0034/4 + flow/4 + i)

#define DP_CSC_A_0(flow)    (0x0044/4 + flow/4)

#define DP_CSC_A_1(flow)    (0x0048/4 + flow/4)

#define DP_CSC_A_2(flow)    (0x004C/4 + flow/4)

#define DP_CSC_A_3(flow)    (0x0050/4 + flow/4)

#define DP_CSC_0(flow)        (0x0054/4 + flow/4)

#define DP_CSC_1(flow)        (0x0058/4 + flow/4)

3.10.17:

#define IPU_DP_REG(offset)        (offset)

#define DP_SYNC                0

#define DP_ASYNC0            0x60

#define DP_ASYNC1            0xBC

#define DP_COM_CONF(flow)        IPU_DP_REG(flow)

#define DP_GRAPH_WIND_CTRL(flow)    IPU_DP_REG(0x0004 + (flow))

#define DP_FG_POS(flow)            IPU_DP_REG(0x0008 + (flow))

#define DP_GAMMA_C(flow, i)        IPU_DP_REG(0x0014 + (flow) + 4 * (i))

#define DP_GAMMA_S(flow, i)        IPU_DP_REG(0x0034 + (flow) + 4 * (i))

#define DP_CSC_A_0(flow)        IPU_DP_REG(0x0044 + (flow))

#define DP_CSC_A_1(flow)        IPU_DP_REG(0x0048 + (flow))

#define DP_CSC_A_2(flow)        IPU_DP_REG(0x004C + (flow))

#define DP_CSC_A_3(flow)        IPU_DP_REG(0x0050 + (flow))

#define DP_CSC_0(flow)            IPU_DP_REG(0x0054 + (flow))

#define DP_CSC_1(flow)            IPU_DP_REG(0x0058 + (flow))

does kernel 3.0.35 initialize IPU wrong? and if not, why the value need to divided by 4?

[wallyyeh]

ok, I found the commit of this:

ENGR00293235 IPUv3: Refine register access

but still not understand the meaning "This makes the register offset values shrink 4 times"

register is 32 bit, ipu->reg_base is defined as u32. so they should be matched. why shrink 4 times?

[alejandrolozan1 · Accepted solution]

Hi Wally,

"The original IPUv3 driver uses readl()/writel() to access the IPUv3 registers in the following way where ipu->reg_base is a pointer which points to a 32 bit I/O memory cell of a certain IPUv3 deblock's base address: writel(value, ipu->reg_base + offset); readl(ipu->reg_base + offset); "

Refers only to pointer aritmethic. If ipu->reg_base is a 32bit pointer, when you add an offet, the address will increment 4 times the offsset.

/Alejandro

[wallyyeh]

Thanks! your answer is so sweet. :smileygrin: