video path question of IMX6D/Q

[Issac_20200908]

Hi,

   In IMX6D/Q reference manual ch19 & 20, the following video data path is shown:

MIPI CSI(VC0~4) ->IPU0&1->SocMUX->LVDS0&1.

   We need two video streams running at the same time.

(1)MIPI VC0&1 ->IPU0->LVDS0

(2)MIPI VC2&3->IPU1->LVDS1

   Can it be implemented by IM6D/Q HW/SW?

[Issac_20200908]

Hi,

   In IMX6D/Q reference manual ch19 & 20, the following video data path is shown:

MIPI CSI(VC0~4) ->IPU0&1->SocMUX->LVDS0&1.

   We need two video streams running at the same time.

(1)MIPI VC0&1 ->IPU0->LVDS0

(2)MIPI VC2&3->IPU1->LVDS1

   Can it be implemented by IM6D/Q HW/SW?

[joanxie · Accepted solution]

yes, imx6q can support this, for support dual mipi, you can refer to the link as below:

https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/iMX6DQ-MAX9286-MIPI-CSI2-720P-camera-sur...

for support dual lvds, you can use spilit mode or dual mode