var_som_mx6, core resetting when reading from peripheral memory address

[ameerhamza]

Dear all,

I am using var_som_mx6, which inherits a imx6 quad core processor (same as sabre lite). When i trying to read peripheral memory (suppose i'm trying to read peripheral memory of I2C1) the core resets. Attached is the image which clearly shows my problem. Could any one please explain the reason of CPU resetting, or any way to solve this problem. Thank you in advance.

Best Regards,

Hamza.

[ameerhamza]

Dear igor,

I want to ask one more thing, The memory space between UART register is 40 bytes. E.g UART1_URXD is at 0x2020000 and UART1_UTXD is at 0x2020040. And in between reserved fields memory read is not allowed either, and if we read core resets. Is there any reason why we are wasting this 36 bytes. Thanks in advance.

Best regards,

Hamza

[igorpadykov · Accepted solution]

Hi Hamza

you are right I2C contains 16-bit registers so one can try md.w.

Memory space of UART and other levels is defined at system level.

Best regards
igor
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[ameerhamza]

Dear igor,

Your quick response is always appreciated. If i read CCM_CCGR2 register core resets, however i forcefully write all f's to the register and i am sure to some extent that clocks are enabled. The strange part is that if i connect segger j-link and read the same register 0x21a0000 it does not read, but if i use mem16 leave upper two bytes it gives me the correct values. Since I2C and UART both are 16 bits registers, i think reading 32 bits create some problems, right ? Please correct me if i am wrong. Thank you very much again for you timely reply.

Best regards,

Hamza

[igorpadykov]

Hi Hamza

one can check if i2c1 clock is enabled in register CCM_CCGR2
and try to access to it with jtag. May be useful to check power supplies
according to rules given in i.MX6 System Development User’s Guide
http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf

Best regards
igor
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