using mipi dsi for LCD display on imx6dl about android

[tangyuan]

HI:

   I am using a mipi dsi for lcd display on imx6dl about android.I have some problems to ask. I use the below pins:

   DSI_D0M

   DSI_D0P

   DSI_CLK0P

   DSI_CLK0M

   DSI_D1M

   DSI_D1P

   firstly,i can't find the special pin definition in iomux-6dl.h

   secondly, i would like to know how to set the UBOOT parameters.

   thirdly,  How can i modified the kernel to do the mipi lcd.

   Can you anyone help me!

[qiang_li-mpu_se · Accepted solution]

The MIPI DSI pins have no IOMUX, they are fixed for MIPI display.

Freescale verified mipi display: drivers\video\mxc\mxcfb_hx8369_wvga.c

video=mxcfb0:dev=mipi_dsi,TRULY-WVGA,if=RGB24

[juliocruz]

Dear Qiang Li,

I follow the suggestions from you and Tang to setup the timing in a MIPI-DSI panel.

For now, I can communicate with the panel controller in the "setup" functions at file mxcfb_hx8369_wvga.c (command mode). For example, I can get the status and config other registers.

However, the display don't show anything (video mode).

According with the panel controller, the clock period in HS mode must be greater than 4ns however in the scope I get 3ns. So, I think this could be the problem. To change this clock using the mipi_dsi driver, I change the variable "max_phy_clk", however, after this change, the LP clock is also changed and I cannot setup the panel register (in LP mode).

Do you have any suggestions? For example, can I change the HS and LP clock independently?

Thanks,

JC

[tommalnar]

Julio/NXP, did you ever find resolution to this issue?  I am trying to run a HX8363-A instead of a HX8369.  Although similar in number the command set is completely different between displays.  I created my own driver for HX8363-A and I can communicate in command mode.  I have verified on the screen that the settings are taking and I can read back correct values.  When I switch to video mode nothing is showing up. 

It seems PHY clock in video mode should be 250Mhz based on the documentation.  However I find I can only communicate with the device in LP command mode when the max PHY clock setting is between 650-1000.   Below 650 starts to get packet timeouts and settings don't take.

The documentation for the HX8363 also states commands are sent in HS video mode only.  I'm not sure if that is a typo or true, but that would mean I shouldn't be using command mode at all and just injecting my setup packets in video mode .  Is that even possible on the i.MX6?  I tried simple commands like sleep out (11h) in video mode at 250Mhz PHY clock and they don't work.  However they don't error either. 

[qiang_li-mpu_se]

If PHY clock was changed, you can try to change the followed setting, for example:

-#define DSI_CLKMGR_CFG_CLK_DIV  (0x107)
+#define DSI_CLKMGR_CFG_CLK_DIV  (0x104)

TX_ESC clock and the MIPI LP clock are the same thing, so DSI_CLKMGR_CFG_CLK_DIV is used to control the LP clock frequency.

TX_ESC clock = PHY byte clock / (DSI_CLKMGR_CFG_CLK_DIV & 0xFF).

[tommalnar]

Thank you so much Qiang Li!

That explains things and its now working for me.  I can lower the clock to 240Mhz and set DSI_CLKMGR_CFG_CLK_DIV to 0x102 which is what the device likes in command mode and video mode.  

I just want to say the support from NXP in my experience is outstanding.  I hope your manager receives this message.

[tangyuan]

HI:

    qiang,Thank you very much.

    1.Your said:The MIPI DSI pins have no IOMUX.Your mean that I don't need defining pins in board-mx6dl_sabresd.c
 

    2.Before i do the lcd ,i remembered that i modified in below files:

    board-mx6q_sabresd.c and mxc_lcdif.c

     I  put the LCD timing parameters in the file:mxc_lcdif.c

     just a example.

{

/* 800x480 @ 57 Hz , pixel clk @ 27MHz */

"CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10,

FB_SYNC_CLK_LAT_FALL,

FB_VMODE_NONINTERLACED,

0,},

  The word:Freescale verified mipi display: drivers\video\mxc\mxcfb_hx8369_wvga.c

  It told me that i need putting the mipi lcd timing parameters in the file mxcfb_hx8369_wvga.c?

static struct fb_videomode truly_lcd_modedb[] = {

{

  "TRULY-WVGA", 64, 480, 800, 37880,

  8, 8,

  6, 6,

  8, 6,

  FB_SYNC_OE_LOW_ACT,

  FB_VMODE_NONINTERLACED,

  0,

},

};  This struct was defined in the file mxcfb_hx8396_wvga.c

                                                                                                                                                                                                                      Best Regards

[qiang_li-mpu_se]

Yes, you don't need defining pins in board-mx6dl_sabresd.c for mipi display.

And for mipi display, mxc_lcdif.c will not be used, you should reference to mxcfb_hx8369_wvga.c to implement a driver for your panel. Just modify the timing parameters in mxcfb_hx8369_wvga.c is not enough, the mipi display initialization codes are depends on panel, it is not common code for all panels.

[tangyuan]

HI:

   qiang:

   I have a little understood.

   Firstly, i need to implement a driver for my panel reference to mxcfb_hx8369_wvga.c.

   Secondly, i think that in board-mx6q_sabresd.c if i need do as follows:

  
   static struct mipi_dsi_platform_data mipi_dsi_pdata = {

.ipu_id  = 0,  

.disp_id = 1,

.lcd_panel = "TRULY-WVGA",

.reset  = mx6_reset_mipi_dsi,

};

static void mx6_reset_mipi_dsi(void)
{
gpio_set_value(SABRESD_DISP_PWR_EN, 1);
gpio_set_value(SABRESD_DISP_RST_B, 1);
udelay(10);
gpio_set_value(SABRESD_DISP_RST_B, 0);
udelay(50);
gpio_set_value(SABRESD_DISP_RST_B, 1);

/*
  * it needs to delay 120ms minimum for reset complete
  */
msleep(120);
}

I would like to ask the mipi_dsi_pdata can be defined above,

I feel that mx6_reset_mipi_dsi is necessary.

Because I guess  the RST_B and PWR EN is for my mipi lcd panel