uboot logo color is not normal

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uboot logo color is not normal

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fulinux
Contributor IV

Dear Community,

board: imx6q;

version: u-boot-2009.08;

i did what this doc said: https://community.nxp.com/docs/DOC-98109

but the logo color is not normal, it si green like this:

P60512-190156.jpg

what is wrong? and this is my head file:

    //#define IPU_OUTPUT_MODE_HDMI

    #define IPU_OUTPUT_MODE_LVDS

//  #define IPU_OUTPUT_MODE_LCD

#ifdef IPU_OUTPUT_MODE_LVDS

    // For LVDS, 1920*1080 resolution, dual channel

    #define DISPLAY_WIDTH   1920

    #define DISPLAY_HEIGHT  1080

    #define DISPLAY_BPP     32

    #define DISPLAY_IF_BPP  24  // RGB24 interface

    #define DISPLAY_HSYNC_START 80

    #define DISPLAY_HSYNC_END       68

    #define DISPLAY_HSYNC_WIDTH 12

    #define DISPLAY_VSYNC_START 15

    #define DISPLAY_VSYNC_END   15

    #define DISPLAY_VSYNC_WIDTH 8

#define DISPLAY_PIX_CLOCK   139526400  //(DISPLAY_HSYNC_START + DISPLAY_HSYNC_END + DISPLAY_HSYNC_WIDTH + DISPLAY_WIDTH) *   

(DISPLAY_VSYNC_START + DISPLAY_VSYNC_END + DISPLAY_VSYNC_WIDTH + DISPLAY_HEIGHT) * refresh rate (60Hz)

    #define LVDS_SPLIT_MODE  // For dual channel split mode.

    #define DISPLAY_VSYNC_POLARITY          1

    #define DISPLAY_HSYNC_POLARITY          1

    #define DISPLAY_CLOCK_POLARITY          1

    #define DISPLAY_DATA_POLARITY               0

    #define DISPLAY_DATA_ENABLE_POLARITY        1

    #define IPU_NUM         1  // 1 for IPU1, 2 for IPU2.

    #define DI_NUM          0  // 0 for DI0, 1 for DI1.

    #define LVDS_PORT       0  // 0 for LVDS0, 1 for LVDS1.

    #define DI_CLOCK_EXTERNAL_MODE  //When clock external mode was defined, the DI clock root will be PLL3 PFD1,

                                //without this macro, the DI root clock is IPU internal clock.

nothing changed, just above, can you help me? what should i do? what is info do you need? tell me.

wating for your reply?

thank you.

fulinux.

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qiang_li-mpu_se
NXP Employee
NXP Employee

I had identified the issue, please apply the attached uboot patch to fix it.

it is based on JB4.3_1.1.1_uboot_logo_keep_patch_2015-09-18.zip

View solution in original post

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fulinux
Contributor IV

Dear all,

     thank you Qiang and jie jia.

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qiang_li-mpu_se
NXP Employee
NXP Employee

I had identified the issue, please apply the attached uboot patch to fix it.

it is based on JB4.3_1.1.1_uboot_logo_keep_patch_2015-09-18.zip

View solution in original post

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fulinux
Contributor IV

Hi Qiang,

I have ported U-Boot-2014.04, and patched L3.10.53_GA1.1.0 patchs, problem still as same as before.

here is code of uboot-2014.04:

http://yun.baidu.com/share/link?shareid=3786656888&uk=3358806299

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qiang_li-mpu_se
NXP Employee
NXP Employee

Please attach your modified code here.

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fulinux
Contributor IV

Hi Qiang,

can you download my code from baidu yun? do you want anything else? pls tell me

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jiejia
Contributor III

你好,我遇到了和你一模一样的问题。你要是不介意的话,能帮忙测试一下你的LVDS的时钟频率吗?我这边修改DISPLAY_PIX_CLOCK的值,但是LVDS的时钟频率一直都是75M左右。

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qiang_li-mpu_se
NXP Employee
NXP Employee

If your panel needs pricise pixel clock, you should apply 0002-Support-LVDS-clock-source-from-PLL5.patch to set PLL5 as the clock source of LVDS.

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jiejia
Contributor III

Dear Qiang,

    你好,我按照JB4.3_1.1.1_uboot_logo_keep_patch_2015-09-18.zip里面的补丁,修改了static int config_lvds_clk(u32 di, u32 ref, u32 freq),现在时钟是正常了。但是显示屏上还是隔列的数据是白色的情况。

   然后,我在u-boot阶段和内核启动之后,都把fb的数据设置为全0,所以数据输出应该是一样的。我量了一下LVDS的信号,其它的信号跟内核启动成功后的信号都是一样的,但是在u-boot阶段发现LVDS1_TX3_N和LVDS1_TX3_P一直都是低电平。你能帮忙解答一下吗?

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qiang_li-mpu_se
NXP Employee
NXP Employee

The LVDS TX3 data lanes depend on your DISPLAY_IF_BPP setting, when it is 18, there is no signal on LVDS TX3. So you should set it to 24:

#define DISPLAY_IF_BPP 24

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fulinux
Contributor IV

Hi Qiang,

jie jia says is right, both he and i found that it is little white not black when we write 0x00 to whole fb memory, and if you look at screen carefully, we found one column black and one column white appear alternately, photos taken by mobile can't shows this details, but you can see that if you enlarge photos:

P60513-154733.jpg

Enlarge picture like this:

QQ截图20160517122819.png

i don't know if you know what i mean. we think this patch has some bug, we need you to solve this problem.

thank you!

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jiejia
Contributor III

Would you give me a link for 0002-Support-LVDS-clock-source-from-PLL5.patch. I don't need a pricise pixel clock, but the pixel clock should not always 75Mhz.

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fulinux
Contributor IV

Hi Qiang,

Have you read my code, have you find any wrong place?

i found this:

board/freescale/mx6q_sabresd/mx6q_sabresd.c:

2156 #ifdef CONFIG_UBOOT_LOGO_ENABLE

2157 #ifdef IPU_OUTPUT_MODE_LVDS

2158     ipu_iomux_config(); // here no this line before, should we add this function?

2159     setup_lvds_iomux();

2160 #endif

2161

2162 #ifdef IPU_OUTPUT_MODE_LCD

2163     ipu_iomux_config();

2164     setup_lcd_iomux();

2165 #endif

2166

2167 #ifdef IPU_OUTPUT_MODE_HDMI

2168     setup_hdmi_iomux();

2169 #endif

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fulinux
Contributor IV

tell me you qq

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jiejia
Contributor III

741961278

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fulinux
Contributor IV

Hi,

i can't attach my uboot code here, because 90M+  is big for fsl community. i have uploaded to baidu yun, you can download from here:

http://yun.baidu.com/share/link?shareid=1085957652&uk=3358806299

thank you,

fulinux.

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jiejia
Contributor III

I found this issue, but I don't know how to solve it.

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fulinux
Contributor IV

hi,

i want try  uboot-2015.04(on branch imx_v2015.04_4.1.15_1.0.0_ga), should i need any logo patchs for this version uboot?

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qiang_li-mpu_se
NXP Employee
NXP Employee

Uboot version should not be related to this issue, I think you need find out the different setting between kernel and Uboot.

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fulinux
Contributor IV

Hi Qiang,

someone tell me it is problem of alpha and transparency, is it right?

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qiang_li-mpu_se
NXP Employee
NXP Employee

No, there is no alpha and transparency setting in uboot. How about your kernel to show the same bmp file?

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