i did what this doc said: https://community.nxp.com/docs/DOC-98109
but the logo color is not normal, it si green like this:
what is wrong? and this is my head file:
// #define IPU_OUTPUT_MODE_LCD
// For LVDS, 1920*1080 resolution, dual channel
#define DISPLAY_WIDTH 1920
#define DISPLAY_HEIGHT 1080
#define DISPLAY_BPP 32
#define DISPLAY_IF_BPP 24 // RGB24 interface
#define DISPLAY_HSYNC_START 80
#define DISPLAY_HSYNC_END 68
#define DISPLAY_HSYNC_WIDTH 12
#define DISPLAY_VSYNC_START 15
#define DISPLAY_VSYNC_END 15
#define DISPLAY_VSYNC_WIDTH 8
#define DISPLAY_PIX_CLOCK 139526400 //(DISPLAY_HSYNC_START + DISPLAY_HSYNC_END + DISPLAY_HSYNC_WIDTH + DISPLAY_WIDTH) *
(DISPLAY_VSYNC_START + DISPLAY_VSYNC_END + DISPLAY_VSYNC_WIDTH + DISPLAY_HEIGHT) * refresh rate (60Hz)
#define LVDS_SPLIT_MODE // For dual channel split mode.
#define DISPLAY_VSYNC_POLARITY 1
#define DISPLAY_HSYNC_POLARITY 1
#define DISPLAY_CLOCK_POLARITY 1
#define DISPLAY_DATA_POLARITY 0
#define DISPLAY_DATA_ENABLE_POLARITY 1
#define IPU_NUM 1 // 1 for IPU1, 2 for IPU2.
#define DI_NUM 0 // 0 for DI0, 1 for DI1.
#define LVDS_PORT 0 // 0 for LVDS0, 1 for LVDS1.
#define DI_CLOCK_EXTERNAL_MODE //When clock external mode was defined, the DI clock root will be PLL3 PFD1,
//without this macro, the DI root clock is IPU internal clock.
nothing changed, just above, can you help me? what should i do? what is info do you need? tell me.
wating for your reply?
Solved! Go to Solution.
I have ported U-Boot-2014.04, and patched L3.10.53_GA1.1.0 patchs, problem still as same as before.
here is code of uboot-2014.04:
If your panel needs pricise pixel clock, you should apply 0002-Support-LVDS-clock-source-from-PLL5.patch to set PLL5 as the clock source of LVDS.
你好，我按照JB4.3_1.1.1_uboot_logo_keep_patch_2015-09-18.zip里面的补丁，修改了static int config_lvds_clk(u32 di, u32 ref, u32 freq)，现在时钟是正常了。但是显示屏上还是隔列的数据是白色的情况。
The LVDS TX3 data lanes depend on your DISPLAY_IF_BPP setting, when it is 18, there is no signal on LVDS TX3. So you should set it to 24:
#define DISPLAY_IF_BPP 24
jie jia says is right, both he and i found that it is little white not black when we write 0x00 to whole fb memory, and if you look at screen carefully, we found one column black and one column white appear alternately, photos taken by mobile can't shows this details, but you can see that if you enlarge photos:
Enlarge picture like this:
i don't know if you know what i mean. we think this patch has some bug, we need you to solve this problem.
Would you give me a link for 0002-Support-LVDS-clock-source-from-PLL5.patch. I don't need a pricise pixel clock, but the pixel clock should not always 75Mhz.
Have you read my code, have you find any wrong place?
i found this:
2156 #ifdef CONFIG_UBOOT_LOGO_ENABLE
2157 #ifdef IPU_OUTPUT_MODE_LVDS
2158 ipu_iomux_config(); // here no this line before, should we add this function?
2162 #ifdef IPU_OUTPUT_MODE_LCD
2167 #ifdef IPU_OUTPUT_MODE_HDMI
i can't attach my uboot code here, because 90M+ is big for fsl community. i have uploaded to baidu yun, you can download from here: