uboot - imx9 Ethernet FEC with qca8337

[DavidFlir]

For an iMX91 processor I fail to initialize the FEC ethernet.

1st in the .dtsi

&lpi2c3 {
	bootph-pre-ram;
	bootph-some-ram;
	pca95x: gpio@38 {
			compatible = "nxp,pca9554";
			reg = <0x38>;
			pinctrl-names = "default";
			gpio-controller;
		};

};

&fec {
	compatible = "fsl,imx91-fec", "fsl,imx93-fec", "fsl,imx8mq-fec";
	phy-reset-gpios = <&pca95x 1 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <15>;
	phy-reset-post-delay = <100>;
};

 Then in the .dts

/* Ethernet device */

&fec {
	phy-handle = <&ethphy1>;
	phy-mode = "rgmii";
	pinctrl-0 = <&pinctrl_fec>;
	pinctrl-1 = <&pinctrl_fec_sleep>;
	pinctrl-names = "default", "sleep";
	status = "okay";

	compatible = "qca,qca8337";
	reset-gpios = <&pca9554 1 GPIO_ACTIVE_LOW>; // pin number 1 on mux PCA9554
	reg = <0x10>;
	ports {
		#address-cells = <1>;
		#size-cells = <0>;
		ethphy1: ethernet-phy@2 {
			reg = <0>;
			label = "cpu";
			// ethernet = <&gmac0>; // to do
			phy-mode = "rgmii";
			fixed-link {
				speed = <1000>;
				full-duplex;
			};
		};
	};
};

In have the uboot debug enable for gpio-uclass.c and see in the console

gpio_request_tail: Node 'ethernet@42890000', property 'phy-reset-gpios', failed to request GPIO index 0: -16

FEC MXC: Timeout resetting chip

So it look like configuration for the 'phy-reset-gpios' is not correct  
And the Timeout from the reset...

Later uin uboot I get

Warning: ethernet@42890000 (eth0) using random MAC address - 6a:f5:a4:67:87:8d
eth0: ethernet@42890000

but trying a dhcp result in a coredump.

Any hints are welcome.


I also tried the dts example code like this, but that gives even more errors like `Could not get PHY for FEC0: addr 16`

&fec {
	phy-mode = "rgmii";
	pinctrl-0 = <&pinctrl_fec>;
	pinctrl-1 = <&pinctrl_fec_sleep>;
	pinctrl-names = "default", "sleep";
	fsl,magic-packet;
	status = "okay";

	mdio {
			#address-cells = <1>;
			#size-cells = <0>;
			clock-frequency = <2500000>;

			switch@10 {
				compatible = "qca,qca8337";
				reg = <0x10>;
				ports {
						#address-cells = <1>;
						#size-cells = <0>;

						port@0 {
								reg = <0>;
								label = "cpu";
								ethernet = <&fec>;
								phy-mode = "rgmii";

								fixed-link {
										speed = <1000>;
										full-duplex;
								};
						};
					};
			};
	};
};

[DavidFlir · Accepted solution]

I have solved this issue with removing the line

pinctrl-1 = <&pinctrl_fec_sleep>;

from the dts.. 

It seems the pins were configured for sleeping.

[DavidFlir]

Additional info, the mdio communication seems ok.

fec_mdio_read: phy: 00 reg:02 val:0x1
fec_mdio_read: phy: 00 reg:03 val:0xd036
fec_mdio_write: phy: 00 reg:00 val:0x8000
fec_mdio_read: phy: 00 reg:00 val:0xffff
fec_mdio_read: phy: 00 reg:00 val:0xffff
fec_mdio_read: phy: 00 reg:00 val:0xffff
fec_mdio_read: phy: 00 reg:00 val:0xffff
fec_mdio_read: phy: 00 reg:00 val:0xffff
fec_mdio_read: phy: 00 reg:00 val:0x3100
fec_mdio_read: phy: 00 reg:01 val:0xffff
fec_mdio_read: phy: 00 reg:0f val:0x2000
fec_mdio_read: phy: 00 reg:04 val:0xffff
fec_mdio_write: phy: 00 reg:04 val:0xf1ff
fec_mdio_read: phy: 00 reg:01 val:0x7949
fec_mdio_read: phy: 00 reg:09 val:0xffff
fec_mdio_write: phy: 00 reg:09 val:0xfeff
fec_mdio_read: phy: 00 reg:00 val:0x3100
fec_mdio_write: phy: 00 reg:00 val:0x3300


u-boot=> mdio list
FEC0:
0 - Generic PHY <--> ethernet@42890000

[joanxie]

based on the print information, mdio recognize the PHY under FEC0, but I checked your dts, I suggest that you can refer to the imx91 dtsi files, you need add phy-handle in the fec node, and the driver for fec is compatible = "fsl,imx91-fec", "fsl,imx8mp-fec", "fsl,imx8mq-fec";

&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy2>;
fsl,magic-packet;
status = "okay";

mdio {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;

ethphy2: ethernet-phy@2 {
reg = <2>;
eee-broken-1000t;
};
};
};

and you also can refer to the enclosed file for how to configure rgmii mode, in your first dts,  the reg should be 2

ethphy1: ethernet-phy@2 {
			reg = <0>;

[joanxie]

which bsp version do you use? let me double check it

[DavidFlir]

I am compiling uboot on branch lv_v2025.04 https://github.com/nxp-imx/uboot-imx.
Then I generate my flash.bin with mkimage.

I am actually doubting if there is support for the qualcom pca8337 in uboot..

[joanxie]

how did you connect qca8337 with your imx91 on HW? pls share the HW connection, let me double check it

[DavidFlir]

The first important measurement was on the MDIO line where the configuration steps take place of the Phy.  There was no data and a terrible clock signal.

We did not have a pull-up resistor on MDIO, adding a 1k5 resistor initiated the communication.

Now I see some terrible communication... which fails every 2nd try.

u-boot=> mii read 0 1
fec_mdio_read: phy: 00 reg:01 val:0x7949
7949
u-boot=> mii read 0 1
fec_mdio_read: phy: 00 reg:01 val:0xffff
FFFF
u-boot=> mii read 0 1
fec_mdio_read: phy: 00 reg:01 val:0x7949
7949
u-boot=> mii read 0 1
fec_mdio_read: phy: 00 reg:01 val:0xffff
FFFF
u-boot=> mii read 0 1
fec_mdio_read: phy: 00 reg:01 val:0x7949
7949

So the data 0x7949 is correct, but only every 2nd read... So there is still something wrong there. The data should be always readable without a retry!

[DavidFlir]

Attached you can see the qca8337 and the imx91 connecting part...  No idea if this would give you any additional insight.

What I can add is that I measured the `RX_CLK0` on the qca8337 chip and there is not coming anything in... so communication is impossible. On the other hand the clock for the qca is 25Mhz oscillator and is ok (As well as the Reset signal is not pulled low and measures ok).