u-boot for custom board based on MX6SLEVK with DDR3

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u-boot for custom board based on MX6SLEVK with DDR3

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Jon_Bagg
Contributor III

Two questions

 

1. What register programming aid spreadsheet should I be using for a custom board based on MX6SLEVK with DDR3.  (MX6SLEVK uses LPDDR2)?

i.MX6SX DDR3 Register Programming Aid

(The file name is MX6SX but the title is MX6SL)

 

2. Which u-boot board should I start from

 

mx6slevk or mx6sxsabersd

 

When I try to usb load u-boot with it's imximage.cfg updated form the spreadsheet....

./imx_usb -v ../p100_u-boot/u-boot.imx

loading binary file(../p100_u-boot/u-boot.imx) to 877ff400, skip=0, fsize=38c00 type=aa

<<<232448, 232448 bytes>>>

succeeded (status 0x88888888)

!!!!mismatch

 

Memory schematic and cfg file attached.

 

DDR3 info

32-bits

2x MT41J64M16JT-15E:G

Original Attachment has been moved to: imximage.cfg.zip

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igorpadykov
NXP Employee
NXP Employee

Hi Jonathan

1.

i.MX6SL DDR3 Register Programming Aid

2. for mx6slevk one needs to use uboot generated for mx6slevk,

please try demo images on link below

i.MX 6SoloLite Evaluation Kit|Freescale

note, if this is custom board, one needs to obtain new ddr setings

running DDR test and rebuild uboot with them

https://community.freescale.com/docs/DOC-96412

Best regards

igor

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igorpadykov
NXP Employee
NXP Employee

Hi Jonathan

1.

i.MX6SL DDR3 Register Programming Aid

2. for mx6slevk one needs to use uboot generated for mx6slevk,

please try demo images on link below

i.MX 6SoloLite Evaluation Kit|Freescale

note, if this is custom board, one needs to obtain new ddr setings

running DDR test and rebuild uboot with them

https://community.freescale.com/docs/DOC-96412

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

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Jon_Bagg
Contributor III

I have tried three different inc files from in DDR_Stress_Tester_V1.0.3.  All three hang when the calibration starts.  Bad hardware / design?

MX6SL_MMDC_DDR3_register_programming_aid_v0.5.inc

MX6Solo_SabreSD_DDR3_register_programming_aid_v0.4.inc

MX6SX_SDB_DDR3_400MHz_Rev1.inc

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Jon_Bagg
Contributor III

Update -> I tried MX6SL_MMDC_DDR3_register_programming_aid_v0.5.inc again and the mem config ran.

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igorpadykov
NXP Employee
NXP Employee

you should use

MX6SL_MMDC_DDR3_register_programming_aid_v0.7.xlsx

and create new *.inc file for custom board.

Last two files are for different processors, not i.MX6SL.

~igor

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Jon_Bagg
Contributor III

Igor,

I'm trying to boot the kernel now, and it hangs very early on.  I've enabled early printk, but I still get nothing.  The DDR memory tester passes tests almost to 600Mhz.  In another post, I see you mentioned about a fuse setting for memory map below but all references to BOOT_CFG3 in the fusemap section in the MX6SL manual say reserved.

Re: IMX6SL kernel hang, linux kernel(3.0.35)

BOOT_CFG3[5-4] configure the lpddr2 mapping mode

'00' Single channel

‘01’ for “Fixed 2x32 map”

'10’ for “4KB interleaving” mode

U-Boot 2014.10-00003-g348bc27-dirty (Aug 06 2015 - 16:01:12)

CPU:   Freescale i.MX6SL rev1.2 at 792 MHz

Reset cause: POR

Board: MX6SLEVK

DRAM:  256 MiB

MMC:   FSL_SDHC: 0

In:    serial

Out:   serial

Err:   serial

Net:   FEC [PRIME]

Error: FEC address not set.

Hit any key to stop autoboot:  0

=> setenv bootargs 'console=ttymxc0,115200 root=/dev/mmcblk0p1 earlyprintk=serial,ttymxc0,115200'

=> bootm 0x82000000 - 0x88000000

## Booting kernel from Legacy Image at 82000000 ...

   Image Name:   Linux-3.19.0-00166-g12cb6ec

   Image Type:   ARM Linux Kernel Image (uncompressed)

   Data Size:    4666336 Bytes = 4.5 MiB

   Load Address: 80008000

   Entry Point:  80008000

   Verifying Checksum ... OK

## Flattened Device Tree blob at 88000000

   Booting using the fdt blob at 0x88000000

   Loading Kernel Image ... OK

   Loading Device Tree to 8fc7e000, end 8fc86558 ... OK

Starting kernel ...

Uncompressing Linux...

Kernel was built

export PATH="$PATH:/opt/freescale/usr/local/gcc-4.6.2-glibc-2.13-linaro-multilib-2011.12/fsl-linaro-toolchain/bin/"

export ARCH=arm

export CROSS_COMPILE=arm-none-linux-gnueabi-

export LOADADDR=80008000

make imx_v6_v7_defconfig

make uImage dtbs

uImage is uploaded to 0x82000000

imx6sl-evk.dtb is uploaded to 0x88000000

Same uImage boots fine on the MX6SL-EVK, any ideas?

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fabio_estevam
NXP Employee
NXP Employee

A suggestion: instead of passing "earlyprintk=serial,ttymxc0,115200", pass only "earlyprintk" in the kernel command line.

Then run 'make menuconfig'

Select Kernel Hacking --->

[*] Kernel low-level debugging functions (read help!)      
       Kernel low-level debugging port (i.MX6SL Debug UART)  --->
(1) i.MX Debug UART Port Selection (NEW)                    

[*] Early printk

Regards,

Fabio Estevam

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Jon_Bagg
Contributor III

Passing only "earlyprintk" got some debug info - Thanks!  Most of the time I get

Uncompressing Linux...

Compressed data violation

-- System halted

Sometimes the kernel starts to boot but dies at random places.  Attached are three logs from when the kernel started but crashed at a random place.

I put some code in arch/arm/boot/compressed/misc.c in function decompress_kernel() to print the variables being passed to decompress_kernel()...

input_data = 0x8087A0F4

length (input_data_end - input_data) = 0x004718CA

output_data = 0x80008000

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fabio_estevam
NXP Employee
NXP Employee

Random crashes usually indicate issues with the DDR initialization. Maybe you should review the DDR init in U-boot.

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Jon_Bagg
Contributor III

Is there a way to start the cpu at a slower clock in u-boot?

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JohnBirch
NXP Employee
NXP Employee

If you set BT_FREQ (BOOT_CFG2[2]) = 1 the CPU will boot at 400 MHz as opposed to 800 MHz.

See Table 8-5 in the reference manual.

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Jon_Bagg
Contributor III

John, I think we have a hardware issue.  I have a SAW wave form on VDD_SOC_CAP.  The titanium capacitor on VDD_SOC_CAP was installed backwards.  I quickly looked through the mx6sl's hardware development guide for capacitor requirements for VDD_SOC_CAP.  It only says 22uF and doesn't list a ESR rating.  I'm thinking these 22uF caps should be a ceramic and not a titanium.  It would be nice to know a ESR & capacitance range for VDD_SOC_CAP decoupling.

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JohnBirch
NXP Employee
NXP Employee

With it put in properly does it work OK now?

I’ve had backwards tantalum caps shoot up fireballs, which lets you know there’s a problem ☺

A SAW wave is not right, what voltages does it go up/down to? What is the VDD_SOC look like?

We have been using {CER 22UF 4V 20% X5R 0603} for the 22uF on our boards

Note that you should only have 22uF maximum on the VDD_xxx_CAP lines.

The following is from the Hardware Development Guide.

Best regards,

John

John Birch

Senior Field Applications Engineer

Freescale Semiconductor

john.birch@freescale.com<mailto:john.birch@freescale.com>

416.569.5903

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Jon_Bagg
Contributor III

Yes, the kernel boots now that I changed the caps.  There is no longer a SAW waveform.  Thanks for your help.  For some reason we used a 402 footprint instead of a 603 like the reference design, so we can only get a 402 ceramic up to 10uF.  I'd rather use a ceramic than a tantalum.

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fabio_estevam
NXP Employee
NXP Employee

Glad to know the kernel boots fine now, Jonathan!

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JohnBirch
NXP Employee
NXP Employee

Great. Thanks

John

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Jon_Bagg
Contributor III

Should the DCD be setting up the watchdog?

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Jon_Bagg
Contributor III

Does BOOT_CFG2[2] map to LCD_DAT10 pin?  I set LCD_DAT10 pin high and u-boot still says it is 792 MHz

46.7.2 SRC Boot Mode Register 1 (Pg 2790)

BOOT_CFG2[2] = bit 10

Table 46-1.SRC External Signals (Pg 2770)

says SRC_BOOT_CFG10 = LCD_DAT10

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Jon_Bagg
Contributor III

Yes, it does feel like a memory issue.  I compared my u-boot DCD cfg file to the MX6SL_MMDC_DDR3_register_programming_aid_v0.7.xlsx and they are identical except for the calibration registers I took from the DDR stress tester.  I also compared it to the .inc file from DDR stress tester and everything is identical except for the CS0_END and MMDC0_MDCTL as they have been configured for my board / memory.

Does this spreadsheet generate everything necessary for the DCD? or are there additional registers that need to be configured?

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