stuck in the kernel using trained DDR bin

[peter-vzense]

I use one third-part I.MX8MM board to pre-debug for our project.

this board use DDR4 that is MT40A512M16LY-062E

After the DDR training, I put the ddr4_timing.c into the uboot. After that the uboot works fine, but it stuck in the kernel when the login come out. 

So I have some questions like below:

1. Except changing the ddr timing files in the uboot, which steps need to be done? 

2. In the MX8M_Mini_DDR4_RPA_v15.xlsx, there are only 2 frequency setpoints can be chosen, and only 533 or 668 can be the sencond setpoint value. But in the LPDDR4 RPA, there are 3 setpoints and can set it manually. why have this limitation? if I want to change the setpoints to other value, how can I do that?

3. In the kernel, will the DDR frequncy be changed or not? I do not see any ddr frquency value in the dts file.

[peter-vzense]

this question is about the IMX8MM_EVK, in the uboot code, the ddr4_timing.c have one struct ddr4_dram_fsp_msg that have three rate value config 2400, 400, 100. 

And in the RPA files, there are only two frequency can be set. 

do I need modify the RPA or the uboot code? @igorpadykov 

[peter-vzense]

one more found and share with you, hope can help us find the root.

I just replaced the ddr4_timing.c to the 3rd part timing file in their sdk, after that everything works fine. 

So it seem the ddr timing is the key point. But I found the fsp_table have 3 value that is 2400, 400, 100 in the 3rd part sdk. and in the RPA, there can not be set to there frequncy. 

the code I pushed on the below link, you could reference. @igorpadykov 

https://cowtransfer.com/s/178706385ccf44 

[igorpadykov]

for "3rd part timing file" suggest to apply for help to vendor of that software bsp.

NXP supports only i.MX8M Mini EVK which works fine with configurations defined in

RPA Tool for it   MX8M_Mini_DDR4_RPA_v15.xlsx

NXP linux documentation:

https://www.nxp.com/design/software/embedded-software/i-mx-software/embedded-linux-for-i-mx-applicat...

Best regards
igor

[peter-vzense]

I think NXP is one great IC company not an EVK vendor. You sell the IC itself, not just the EVK.

My question is about the minimum system with the I.MX8MM, not driver development with the board.

As you said, if I have questions on my board with NXP IC, don't you have duty to support?

I apologize in advance if I have some misunderstand. Or do I need to search the support from other way, you could tell us directly. 

@igorpadykov 

[peter-vzense]

add some information.

my board use two 16bit DDR as 32bit, so could you check the parameters in my RPA? is it correct? 

@igorpadykov 

[igorpadykov]

such configuration 2xMT40A512M16LY is used on NXP i.MX8M Mini DDR4 EVK board

i.MX 8M Mini Evaluation Kit DDR4 Design Files

RPA Tool for it   MX8M_Mini_DDR4_RPA_v15.xlsx

So if ddr test passed, no need for modifications in NXP uboot/linux codes for ddr. 

Best regards
igor

[peter-vzense]

just retried this configuration, bad news is having the some issue. 

do you have any idea for this ?

@igorpadykov 

[igorpadykov]

please use common guidelines for DDR4 provided in sect.3.4. DDR design recommendations

i.MX 8M Mini Hardware Developer’s Guide

Best regards
igor

[igorpadykov]

Hi Peter

1. ddr size can be adjusted using #define PHYS_SDRAM_SIZE in

https://source.codeaurora.org/external/imx/uboot-imx/tree/include/configs/imx8mm_evk.h?h=imx_v2020.0...

Also first recommended to try without OP-Tee, use sect.5.6.10 OP-TEE enablement

i.MX Yocto Project User’s Guide​

2. number of setpoints is limited in below codes:

https://source.codeaurora.org/external/imx/uboot-imx/tree/drivers/ddr/imx/imx8m/ddrphy_utils.c?h=imx...

https://source.codeaurora.org/external/imx/uboot-imx/tree/drivers/clk/imx/clk-imx8mm.c?h=imx_v2020.0...

https://source.codeaurora.org/external/imx/imx-atf/tree/plat/imx/imx8m/ddr/clock.c?h=imx_5.4.70_2.3....

3. no

Best regards
igor

[peter-vzense]

Hi Igor,

thank you for you reply.

sorry for the missing msg.

1. I already changed the SDRAM_SIZE based on the board.

2. I do not use the TEE

3. I create one new board based on the imx8mm_evk in uboot, and I changed the ddr4_timing.c(from DDR tool), pmic init code(DDR4 voltage), IMX8M_DDR4 config. And the result is like I said at the beginning.

About my frequncy setpoint question, I don't understand that the evk using LPDDR4 and 100,400,3000 timing table in the timing file, and I change it to the DDR4 with 1066, 2400.

do I need to modify somthing for that? 

Based on your experience, do i miss or do something wrong steps on it?

@igorpadykov  

[igorpadykov]

you wrote:

>I use one third-part I.MX8MM board to pre-debug for our project.
..
>3. I create one new board based on the imx8mm_evk in uboot..

if it is some third party board, you can ask sources for that board from its vendor.

"imx8mm_evk" build machine configuration can not be used for third party board since

it is different from NXP i.MX8M Mini EVK board.

Best regards
igor

[peter-vzense]

The purpose of using this board is preparing for our board that is made with IMX8M chips, and our board is in the works.

I just want to run the minimum system on this board, for this target, the ddr issue seem to be the last problem.

And we also use the DDR4 in our board, so I think it is important to find the solution out.

we could talk about this issue and if it is our board.

So let's focus on the issue itself.