several questions about IPU's DI

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several questions about IPU's DI

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gaoweilin
Contributor I

hi,I like this forum!

here are some questions about IPU's DI:

1:According to the Sabre  reference design ,thers is one parallel RGB displasy interface including  DISP0_DATA(23..0), DISP0_CLK,DISP0_HSYNC,DISP0_VSYNC,DISP0_CNTRST,DISP0_DRDY.What's the meaning of DISP0_CNTRST and DISP0_DRDY?Should  I use  DISP0_DRDY as  data_en?and what does  DISP0_CNTRST mean? can i make the pin DI0_PIN4 which mapped to DISP0_CNTRST unconnected?

DISP0_PIN2 is used as HSYNC,DISP0_PIN3 as vsync, DISP0_PIN15 as DISP0_DRDY, why these pins should be conntected like this? is PIN2 mapped to Hsync in imx6q?

2.Is it possibel to make two channel display work at the same time? for example,connect the IPU1's two DI to external display devices, Are there any other choices? Can hdmi and lvds interface work at the same time, not in  the time sharing mode?

3,what is the soruce of HDMI and LVDS interface? is it IPU's DI? if the answer is YES,then is it impossible to use LVDS or HDMI  and DI''s parallel RGB at the same time?


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qiang_li-mpu_se
NXP Employee
NXP Employee

For Q1:
DISP0_CNTRST was not used in current BSP, this pin was designed to control the backlight, but in current BSP, the PWM pin was used for backlight.
DISP0_DRDY is DE(Display Data Enable)
DISP0_PIN2 is used as HSYNC, DISP0_PIN3 as vsync, DISP0_PIN15 as DISP0_DRDY. For VSYNC, HSYNC and DRDY, they are configable, but in current BSP, they are hardcoded to PIN2, PIN3 and PIN15. For how to change the DI PIN number, you can reference to https://community.freescale.com/thread/279078.
By the way, if you are not familiar with IPU, we don't suggest you to modify the display DI pin usage.

For Q2:
Yes, the dual display use case is OK, the two DIs can work at the same time. It can support two parallel RGB LCD panels; or one LCD + one HDMI; or one LCD + one LVDS; or one HDMI + one LVDS.

For Q3:
The DI is also the source for HDMI and LVDS. For dual display case, it was answered in Q2.

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qiang_li-mpu_se
NXP Employee
NXP Employee

For Q1:
DISP0_CNTRST was not used in current BSP, this pin was designed to control the backlight, but in current BSP, the PWM pin was used for backlight.
DISP0_DRDY is DE(Display Data Enable)
DISP0_PIN2 is used as HSYNC, DISP0_PIN3 as vsync, DISP0_PIN15 as DISP0_DRDY. For VSYNC, HSYNC and DRDY, they are configable, but in current BSP, they are hardcoded to PIN2, PIN3 and PIN15. For how to change the DI PIN number, you can reference to https://community.freescale.com/thread/279078.
By the way, if you are not familiar with IPU, we don't suggest you to modify the display DI pin usage.

For Q2:
Yes, the dual display use case is OK, the two DIs can work at the same time. It can support two parallel RGB LCD panels; or one LCD + one HDMI; or one LCD + one LVDS; or one HDMI + one LVDS.

For Q3:
The DI is also the source for HDMI and LVDS. For dual display case, it was answered in Q2.

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