"System clock cycle" meaning of DC parameter table.

[takayuki_ishii]

Hello community,

I have one question about DC parameter table of datasheet.

In datasheet IMX6DQAEC rev5 09/2017,  footnote 1 of Table 22 say that 

1 Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle.

I think that "system clock cycle" of this comment mean a XTALI input clock cycle.

So that is a calculate as following.

10% of the system clock cycle = 1/24MHz * 10/100 = 4.1nsec

Is ti correct?

Best regards,

Ishii.

[takayuki_ishii]

Hello Yuri,

Thank you for your quick response.

> The overshoot/undershoot period should be less than 10% of shortest possible toggling period of the

> input signal or per input signal specific protocol requirement.

My understanding is a following.

  If we use CSIx_DATx pin as IPU_CSI_DATAx with 27MHz pixel clock.

  It should be less than 10% of 27MHz pixel clock period.

  If we use CSIx_DATx pin as GPIOx_IOxx.

  It should be less than 10% of the XTALI clock period.

Is it correct?

Best regards,

Ishii.

[Yuri]

Hello,

  Your understanding is correct.

Regards,

Yuri.

[takayuki_ishii]

Hello Yuri,

Thank you for your quick response.

I will discuss it by pixel clock period.

Best regards,

Ishii.

[Yuri · Accepted solution]

Hello,

  The overshoot/undershoot period should be less than 10% of shortest possible toggling period of the

input signal or per input signal specific protocol requirement. For GPIO input signal overshoot/undershoot

period, it should be less than 10% of the XTALI period.

Have a great day,

Yuri

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