Hi,
I porting u-boot and kernel to imx6q , the u-boot was start successufl, but the kernel not start.
u-boot version:U-Boot 2014.01
kernel:Linux-3.10.17。
This is starting message:
U-Boot 2014.01-00001-g13e5fd1-dirty (Jul 20 2015 - 16:21:16)
CPU: Freescale i.MX6Q rev1.2 at 792 MHz
Reset cause: POR
Board: MX6-SabreSD
DRAM: 1 GiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
*** Warning - bad CRC, using default environment
No panel detected: default to Hannstar-XGA
Display: Hannstar-XGA (1024x768)
In: serial
Out: serial
Err: serial
Net: Phy not found
PHY reset timed out
FEC [PRIME]
Warning: failed to set MAC address
Hit any key to stop autoboot: 0
mmc2 is current device
reading boot.scr
** Unable to read file boot.scr **
reading uImage
5763944 bytes read in 264 ms (20.8 MiB/s)
Booting from mmc ...
reading imx6q-sabresd.dtb
45548 bytes read in 19 ms (2.3 MiB/s)
## Booting kernel from Legacy Image at 12000000 ...
Image Name: Linux-3.10.17-1.0.0_ga-gdaa28b6-
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 5763880 Bytes = 5.5 MiB
Load Address: 10008000
Entry Point: 10008000
Verifying Checksum ... OK
## Flattened Device Tree blob at 18000000
Booting using the fdt blob at 0x18000000
Loading Kernel Image ... OK
Using Device Tree in place at 18000000, end 1800e1eb
Starting kernel ...
You may need i.MX_BSP_Porting_Guide.pdf (in the L4.1.15_1.1.0_LINUX_DOCS)
i.MX 6Quad SABRE Development Board|NXP
All the best
Jian Jiang
Hi hang
such hanging may indicate DDR errors or incorrect memory configuration,
one can test memory with DDR test
https://community.freescale.com/docs/DOC-96412
Best regards
igor
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Hi,
I have calibration ddr with :
ddr_stress_tester -t mx6x -df MX6Q_SabreSD_DDR3_register_programming_aid_v1.5.inc
but it not work.
still stop at: Starting kernel ...
do you know haveason another re about it ?
thanks !
MX6Q_SabreSD_DDR3_register_programming_aid_v1.5.inc
is for Sabre board and it may not work properly for custom board.
For custom board one needs to get its own parameters using
i.Mx6DQSDL DDR3 Script Aid tool.
In the uboot/arch/arm/cpu/armv7/mx6/soc.c I defined CONFIG_SYS_L2CACHE_OFF macro, off the l2 cache, because of that ?