Hi,
I try to use a parallel LCD panel on i.mx6UL board.
And I change the display timings to a standard VESA timings as the following:
============================================================
display0: display0 {
bits-per-pixel = <32>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <40000000>;
hactive = <800>;
hfront-porch = <40>;
hsync-len = <128>;
hback-porch = <88>;
vactive = <600>;
vfront-porch = <1>;
vsync-len = <4>;
vback-porch = <23>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
================================================================
Then I measure the signal of pixel clock on oscilloscope and get 36 MHz instead of 40 MHz.(It's about 10% errors.)
Then I dump the clock tree information in kernel.
# mkdir -p /tmp/debug
# mount -t debugfs none /tmp/debug/
# cd /tmp/debug/clk
# cat clk_summary
================================================================
pll5_bypass_src 1 1 24000000 0
pll5 1 1 651410064 0
pll5_bypass 1 1 651410064 0
pll5_video 1 1 651410064 0
pll5_post_div 1 1 651410064 0
pll5_video_div 1 1 651410064
lcdif_pre_sel 1 1 651410064
lcdif_pred 1 1 108568344
lcdif_podf 1 1 36189448
lcdif_pix 1 1 36189448
iomuxc 0 0 36189448
lcdif_sel 0 0 36189448
================================================================
The "lcdif_pix" is about 36 MHz.
I also check the mxsfb.c
================================================================
static void mxsfb_enable_controller(struct fb_info *fb_info)
{
ret = clk_set_rate(host->clk_pix,
PICOS2KHZ(fb_info->var.pixclock) * 1000U);
}
static int mxsfb_restore_mode(struct mxsfb_info *host)
{
vmode.pixclock = KHZ2PICOS(clk_get_rate(host->clk_pix) / 1000U);
vmode.hsync_len = get_hsync_pulse_width(host, vdctrl2);
vmode.left_margin = GET_HOR_WAIT_CNT(vdctrl3) - vmode.hsync_len;
vmode.right_margin = VDCTRL2_GET_HSYNC_PERIOD(vdctrl2) - vmode.hsync_len -
vmode.left_margin - vmode.xres;
}
================================================================
The clock frequency of "lcdif_pix" in clock tree is set by reference pixel clock (40 MHz).
Then get the pixel clock frequency from "lcdif_pix" (36 MHz).
I guess this problem results from the clock source(PLL) of pixel clock can't be set precisely.
Am i right ?
For some panels with critical timing, it may run into trouble.
Do you have any suggest to get rid of this problem?
Thank you !
