ov7740 camera with custom i.MX6DL board using CSI0 in HREF (gated clock) mode

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ov7740 camera with custom i.MX6DL board using CSI0 in HREF (gated clock) mode

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thomasquartier
Contributor II

Hi all,

 

I'm using an custom i.MX6S/DL board with an Omnivision ov7740 camera connected through the parallel interface in 8 bit HREF (gated clock) mode.

Connections:

ov7740i.MX6
Y0N.C.
Y1N.C.
Y2CSI0_DAT10
Y3CSI0_DAT11
Y4CSI0_DAT12
Y5CSI0_DAT13
Y6CSI0_DAT14
Y7CSI0_DAT15
Y8CSI0_DAT16
Y9CSI0_DAT17
PCLKCSI0_PIXCLK
HREFCSI0_MCLK
VSYNCCSI0_VSYNC
XCLKGPIO_0
SIOCCSI0_DAT9
SIODCSI0_DAT8

 

I started with the driver posted in the thread below by aurelien bouin.

OV7740 camera on I.MX6 using CSI0 in BT.656 mode

 

I know i should use CSI0_DAT12 - CSI0_DAT19 for 8 bit mode but it is not possible whit the current hardware.

To solve this I'm trying to use CSI0 in 10 bit mode.

 

I changed the device tree:

 

ov7740: ov7740@21 {

    compatible = "ovti,ov7740";

    reg = <0x21>;

    pinctrl-names = "default";

    pinctrl-0 = <&pinctrl_ipu1_2>;

    clocks = <&clks 201>;

    clock-names = "csi_mclk";

    csi_id = <0>;

    mclk = <24000000>;

    mclk_source = <0>;

};

 

v4l2_cap_0 {

  compatible = "fsl,imx6q-v4l2-capture";

  ipu_id = <0>;

  csi_id = <0>;

  mclk_source = <0>;

  status = "okay";

  };

 

ipu1 {

    pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */

    fsl,pins = <

        MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10    0x130B0

        MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11    0x130B0

        MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x130B0

        MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x130B0

        MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x130B0

        MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x130B0

        MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x130B0

        MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x130B0

        MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x130B0

        MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x130B0

        MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x130B0

        MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x130B0

        MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x130B0

        /* MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000 */

        >;

    };

};

 

/* This is default */

ipu1: ipu@02400000 {

    compatible = "fsl,imx6q-ipu";

    reg = <0x02400000 0x400000>;

    interrupts = <0 6 0x4 0 5 0x4>;

    clocks = <&clks 130>, <&clks 131>, <&clks 132>,

    <&clks 39>, <&clks 40>,

    <&clks 135>, <&clks 136>;

    clock-names = "bus", "di0", "di1",

       "di0_sel", "di1_sel",

       "ldb_di0", "ldb_di1";

    resets = <&src 2>;

    bypass_reset = <0>;

};

 

I also made some changes in the ov7740 camera driver:

in the ioctl_g_ifparm function:

  p->u.bt656.frame_start_on_rising_vs = 1;/* Not handled by imx */

  p->u.bt656.bt_sync_correct = 1;  /* Indicate external vsync */

  p->u.bt656.latch_clk_inv = 0; /* 1 : clock on falling edge */

  p->u.bt656.nobt_hs_inv = 0;

  p->u.bt656.nobt_vs_inv = 0;

  p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_10BIT;

  /* p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT; */

  /* p->u.bt656.clock_curr = ov7740_data.mclk;  /* external clock */

 

After building and testing with avconv, the VIDIOC_DQBUF ioctl keeps failing. It looks like there are no interrupts received from the IPU and enc_counter in mxc_v4l2_capture.c is never incremented.

 

The signals on the camera board look OK.

  • MCLK: 24MHz 3,3V
  • All other signals are 1,8V
    • PIXCLK: 24MHz
    • HSYNC 15KHz
    • VSYNC: 30Hz
    • Signals around 12MHz on parallel data lines

 

I've enabled debugging and added the boot output and avconv output as an attachment.

 

Below is a dump of the relevant registers:

IOMUXC_GPR1                                           0x48601005

IOMUXC_GPR13                                         0x0000000C

 

IOMUXC_SW_MUX_CTL_PAD_CSI0_*      0x00000000  (same for all CSI0* pins)

IOMUXC_SW_PAD_CTL_PAD_CSI0_*       0x000130B0 (same for all CSI0* pins)

 

IPU_CONF                                                   0x00000761

IPU_CSI0_SENS_CON                                0x04009900

IPU_CSI0_SENS_FRM_SIZE                      0x01DF027F

IPU_CSI0_OUT_FRM_SIZE                        0x01DF027F

 

I read the BSP porting guide and a some of IPU/camera related posts on this forum.

I also tried different settings, but none of them worked for me.

Any advice?

 

Thanks in advance,

Thomas

Original Attachment has been moved to: output.txt.zip

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5 Replies

144 Views
ankitkumarsingh
Contributor II

Hi Thomas ,

Can u please tell me from where i can get the source code for ov7740 camera module ,

i want to replace the ov5640 with ov7740 .(what other file need to be changed while building the code.)

Is 0v7740 is part of nxp with yocto distribution. 

please provide some guidence .

thanks

Ankit

144 Views
hanseunglee
Contributor III

Hello Thomas

I also want to use csi0 paraller port with gated mode.

If you have soultion, would you share for us?

Best regards,

Han

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144 Views
alejandrolozan1
NXP Employee
NXP Employee

Hi,

I am not an expert on CSI but it seems that you need to use the MSB bits. From RM :

"

In parallel interface a single value arrives in each clock, except when working in BT.1120

mode, in which two values arrive in each cycle. Each value can be 8-16 bit wide

according to configuration of DATA_WIDTH. If DATA_WIDTH is configured to N,

then 20-N LSB bits are ignored."

As far as I understand in BT656 the timing reference signals are embedded in the bus. Therefore if data does not arrive correctly I believe the IPU will not work as expected. Maybe I am misunderstanding but afer checking OV7740 camera on I.MX6 using CSI0 in BT.656 mode  and other discussions the only difference seems to be the connections.

Best Regards,

Alejandro

144 Views
thomasquartier
Contributor II

Hi,

Thanks for your answer.

I'm using HREF (= gated clock) mode instead of BT656 mode.

In this mode the timing signals are not embedded in the data but are triggered by the HSYNC and VSYNC lines.

These signals look OK but there is still no interrupt triggered by the IPU.

Best regards,

Thomas

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alejandrolozan1
NXP Employee
NXP Employee

Got it, but I believe you should still use the MSB as per the RM.

/Alejandro

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